Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
Thread beginning with comment 473950
To view parent comment, click here.
To read all comments associated with this story, please click here.
RE[2]: PowerPC v2 ?
by DeepThought on Fri 20th May 2011 12:50 UTC in reply to "RE: PowerPC v2 ?"
Member since:

Actually the last public Power (now w/o PC) ISA is 2.06.
But it does not describe interrupt handling.
Much of it depends on the implementation. Means IBM does it different from Freescale. And Freescale even has different interrupt handling depending on the core.

Reply Parent Score: 1

RE[3]: PowerPC v2 ?
by Neolander on Fri 20th May 2011 22:00 in reply to "RE[2]: PowerPC v2 ?"
Neolander Member since:

On my first book, it's written "PowerPC User Instruction Set Architecture
Book I
Version 2.02", so I don't have the latest version. This may explain some things.

In the book 3, called "Operating environment architecture", there's a whole chapter (chapter 5) dedicated to interrupt and exception handling. It noticeably mentions an "external" interrupt, that seems to centralize all the external interrupts managed by implementation-specific hardware.

Edited 2011-05-20 22:02 UTC

Reply Parent Score: 1

RE[4]: PowerPC v2 ?
by DeepThought on Sat 21st May 2011 04:56 in reply to "RE[3]: PowerPC v2 ?"
DeepThought Member since:

2.06 differs between -S(erver) and -E(mbedded) Book III
Both have different exception handling.
But common is, that peripheral interrupts are seen to be "extern" to the core.

On Book III-E CPUs (Core + interrupt controller), interrupts often can be routed to either the traditional "External" or to the new "Critical" interrupt.

In a OS environment, the critical interrupt can be used to bypass the OS completely thus running without jitter.

BTW: On ARM cores other then Cortex-M, the behavior is alike. You have the "normal" interrupt and fast interrupts.
Cortex-M is special, as the interrupt controller is part of the core _and_ the core stacks the registers defined as volatile by the ABI (so ARM argues, you need no assembler anymore).

Reply Parent Score: 1