Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
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RE[6]: Locking benchmarks
by Alfman on Tue 24th May 2011 20:32 UTC in reply to "RE[5]: Locking benchmarks"
Alfman
Member since:
2011-01-28

"though it would be difficult to envision a programming model that, with all the callbacks, would make it clear how the program flow goes."

It certainly is different if you're not accustomed to it.
For threads, a linear sequence of events can be visualized easily. (the complexity arises from interaction with other threads).

On the other hand, in the async model, I can look at any single event callback, look at the state of the system and determine exactly where to go from there to get to the next state. Debugging individual callbacks becomes almost trivial. It is far easier to prove correctness under the async model than the thread model.

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