Linked by Thom Holwerda on Tue 25th Oct 2005 18:07 UTC
SUN Microsystems Many of you will remember the fanfare and bravado surrounding Sun Microsystems' Sep. 2004 announcement of a $1 per hour per processor utility computing plan. What you won't remember is Sun revealing a single customer using the service. That's because it hasn't. More than one year since it first started hyping the "pay-for-use grid computing services" Sun is still weeks away from presenting a customer to the public. The program has proved much tougher to sell that Sun ever imagined.
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CharAznable
Member since:
2005-07-06

I don't think Microsoft has anything to do with it. It's not like Sun is a pariah of high-end computing, quite the contrary. I think it's simply a case demand not being as high as expected.

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RE[4]: Is grid technology hyped?
by on Tue 25th Oct 2005 19:44 in reply to "RE[3]: Is grid technology hyped?"
Member since:

I stand corrected. I wonder if its possible for Sun to try running (via emulation/virtual) a x86 instruction set on their upcoming Niagara? Am I way off-base here? Can somebody with more savvy say more? A 8 core with 4 threads per core with low power for x86 is sweet news.

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Dually Member since:
2005-07-26

Nice expensive fast chips used to slowly emulate cheap X86 chips. I must be missing something. I think your off base a bit.

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RE[5]: Is grid technology hyped?
by on Wed 26th Oct 2005 13:49 in reply to "RE[4]: Is grid technology hyped?"
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Not sure what this has to do with story but since you asked.

M core N way threaded processors can use any instruction set, however it makes more sense to use a special purpose ISA to get cost down and performance up. The Sparc & Mips ISAs and others are ameniable to that but I am not sure x86 would make any sense. You end up with lots of slower threads with far greater total throughput than theoretical single threaded designs but each thread on paper can look fairly slow. On the other hand for memory bound apps, x86 performance is way overstated and 1 always waiting slow thread that keeps missing on caches may well be no faster than 1 of many threads in a properly designed MTA. It really all depends on the memory system.

And emulating x86 on Niagara sounds like a really bad idea but its been done before Alpha FX etc and can work. FWIW if I wanted hundreds of HW threads, I absolutely wouldn't want x86 compatibility since there is nothing worth bringing over that can exploit vast concurrency. Highly threaded processors need new (actually 20yrs old) ways of doing things.

transputer guy

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