Linked by Thom Holwerda on Wed 26th Oct 2005 10:51 UTC
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Member since:
2005-07-06
Rayiner pointed out, " I said that x86 isn't the kind of boat-anchor its made out to be."
but only if you have 1 or maybe 2 behind a relatively large cache.
Instruction set architecture is fairly orthogonal to the memory system design, so I don't see what your point is.
If you're really talking about out-of-order vs in-order, well, in-order processors are significantly more sensitive to cache misses.
If one wanted alot more x86 cores, the boat anchor effect comes back in a hurry in several ways no matter how they are implemented.
Why? If x86 costs X% of die space in a one-core design it's still gonna cost X% of die space in an n-core design.