Linked by MOS6510 on Fri 17th May 2013 22:22 UTC
Hardware, Embedded Systems "It is good for programmers to understand what goes on inside a processor. The CPU is at the heart of our career. What goes on inside the CPU? How long does it take for one instruction to run? What does it mean when a new CPU has a 12-stage pipeline, or 18-stage pipeline, or even a 'deep' 31-stage pipeline? Programs generally treat the CPU as a black box. Instructions go into the box in order, instructions come out of the box in order, and some processing magic happens inside. As a programmer, it is useful to learn what happens inside the box. This is especially true if you will be working on tasks like program optimization. If you don't know what is going on inside the CPU, how can you optimize for it? This article is about what goes on inside the x86 processor's deep pipeline."
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RE: Comment by Drumhellar
by tylerdurden on Sat 18th May 2013 01:51 UTC in reply to "Comment by Drumhellar"
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since we're nitpicking, by your own definition the 486 is superscalar; it had multiple functional units.

Superscalar refers to the ability of running multiple functional units (usually redundant ones) in parallel, which I believe the 486 couldn't. The rule of thumb usually is that a superscalar microarchitecture can support theoretical IPCs larger than 1.

Reply Parent Score: 2

RE[2]: Comment by Drumhellar
by butters on Sat 18th May 2013 03:03 in reply to "RE: Comment by Drumhellar"
butters Member since:

Superscalar means multiple instructions may be issued in a single cycle. The P5 Pentium was the first superscalar x86 chip. It could dispatch and issue one or two instructions per cycle in program order. The P6 (Pentium Pro through Pentium III) could dispatch three instructions per cycle and issue five instructions per cycle out of program order.

Pentium M and Core (1) are a direct evolution of P6 with the same three dispatch ports and five issue ports. Pentium M added micro-ops fusion with an additional two pipeline stages (12 to 14). Core allowed two cores to share a common L2 cache.

Core 2, besides the 64-bit GPRs, is wider than P6, with four dispatch ports and six issue ports. And Haswell is adding another two issue ports for a total of eight.

As for pipeline depth, the entire industry has converged on 12-15 cycles for CPUs designed to be clocked in the 2-4GHz range. Apple A6 and Qualcomm Snapdragon have 12-cycle pipelines. Atom is moving from a 14-cycle pipeline to a brand-new 13-cycle pipeline. ARM Cortex A15 has an eponymous 15-cycle pipeline.

But at clock frequencies below ~1.5Ghz, a shorter pipeline is more optimal. The 7-cycle ARM Cortex A7 is the best example of a modern core designed to perform well at low clock frequencies.

Reply Parent Score: 5

RE[2]: Comment by Drumhellar
by theosib on Sat 18th May 2013 03:09 in reply to "RE: Comment by Drumhellar"
theosib Member since:

I'll admit that there is some variation in terminology, but the defining characteristic of a superscalar processor is that it will fetch, decode, and dispatch (queue up to wait for dependencies) multiple instructions on a cycle. It is a partially orthogonal issue that an out-of-order processor may issue (start actually executing) multiple instructions on a cycle due to muliple dependencies being resolved at the same time. There have been plenty of scalar processors with OoO capability (IBM 360 FPU using Tomasulo's algorithm, CDC6600, etc.). And there have been plenty of in-order superscalar processors (original Pentium, original Atom, ARM Cortex A8, various SPARCs, etc.).

I say that these are PARTIALLY orthogonal, because superscalar processors typically have multiple functional units of the SAME type, while scalar processors typically do not. Having the ability to decode multiple instructions at once massively increases the probability that more than one of those will target the same type of functional unit, putting pressure on the execution engine to have redundant functional units to get good throughput.

Out-of-order was developed as a way to decouple instruction fetch from instruction execution. Some instruction types naturally lend themselves to taking multiple cycles (e.g. multiply). Fetch and decode are a precious resource, and you don't want to hold them up just because you have a multiply instruction holding up the works. While that's going on, it would be nice to keep the adder busy doing other independent work, for instance.

So OoO was developed to keep fetch and decode productive. But then that opens up another problem where fetching and decoding one instruction per cycle can't keep the execution units busy. Thence came superscalar. It's an interesting optimization problem to find the right dispatch width and the right number of redundant functional units in order to get the best throughput, especially when power consumption constraints come into play.

Note: I'm a professor of computer science, and I teach Computer Architecture.

Edited 2013-05-18 03:28 UTC

Reply Parent Score: 5

RE[3]: Comment by Drumhellar
by theosib on Sat 18th May 2013 03:44 in reply to "RE[2]: Comment by Drumhellar"
theosib Member since:

Let me put this another way: The number of instructions per clock (IPC) of a scalar in-order processor is much less than 1, because there are many types of multi-cycle instructions. Adding out-of-order allows instruction fetch to continue despite the multi-cycle instructions, as long as those instruction are not dependent on the executing multi-cycle instructions. That brings the IPC closer to 1, but it cannot exceed 1. The objective of Superscalar is to make IPC exceed 1, and it does this, most primarily, by making instruction fetch and decode process multiple instructions per cycle. Whether or not you combine these ideas, superscalar invariably needs to have rendant functional units for some instruction types in order to actually achieve the goal of IPC > 1, in part because the majority of instructons are simple single-cycle integer instructions, so you'll get lots of them together.

Reply Parent Score: 3

RE[3]: Comment by Drumhellar
by Alfman on Sat 18th May 2013 05:22 in reply to "RE[2]: Comment by Drumhellar"
Alfman Member since:


You sound very knowledgeable, certainly more than me. What do you think about cpu cores eventually being replaced / enhanced with massive FPGAs?

The issue I have with current CPU architectures is how there's so much hardware and R&D being thrown at running sequential instruction sets in parallel rather than actually using native parallel instruction sets in the first place. We have undeniably seen dramatic gains for sequential code, and yet, all this focus on sequential code optimization seems to be a major detractor away from what could have been a much better overall strategy for maximizing parallel computation.

For illustrative purposes, take the case of bitcoin mining as good example of a parallel problem where performance is king and software compatibility isn't a factor. The next link contains a sizable dataset very roughly showing how different computational technologies compare:

Intel's latest processors top out at ~65Mhash/s for 6*2 hyperthreaded cores at 200W. As we'll see, the sequential programs running on these super-scalar CPUs cannot compete with real parallel algorithms.

The ARM processors listed top out at ~1Mhash/s running on .5W. If we ran 400 of these to match intel's power consumption, we'd get very roughly 400Mhash/s.

Now when we look at FPGAs, they have 400+ Mhash/s running on less than 20W. If we ran 10 of these to match 200W, we'd get 4000Mhash/s, or 62X the processing power of the x86 cpu.

There are ASICs that have 5000Mhash/s running on 30w (I mention it for comparison only, obviously it's not a reprogrammable part so it wouldn't have a place in a software programmable PC).

While I know CUDA is doing it's part to introduce parallel software to the PC via GPUs, it still fairs poorly compared to the FPGAs. In fact GPU bitcoin miners are throwing in the towel (like CPU miners before them) because electricity costs more than the value of the bitcoins earned.

So in your expert opinion, do you think we're bumping against the wall of diminishing returns with today's superscalar CPUs? Do you see FPGAs as a good contender for even higher performance PCs in the future (assuming we ever get away from sequentially based software programming practices)?

Edit: I realize the numbers are very imprecise and might not even be apples to apples. Never the less bitcoin was the best example I could come up with to compare parallel computation technologies.

Edited 2013-05-18 05:41 UTC

Reply Parent Score: 2