Linked by Thom Holwerda on Wed 22nd Jan 2014 13:47 UTC, submitted by fran
OSNews, Generic OSes

The Muen Separation Kernel is the world's first Open Source microkernel that has been formally proven to contain no runtime errors at the source code level. It is developed in Switzerland by the Institute for Internet Technologies and Applications (ITA) at the University of Applied Sciences Rapperswil (HSR). Muen was designed specifically to meet the challenging requirements of high-assurance systems on the Intel x86/64 platform. To ensure Muen is suitable for highly critical systems and advanced national security platforms, HSR closely cooperates with the high-security specialist secunet Security Networks AG in Germany.

The webpage contains instructions for building the kernel yourself, for installing it in a virtual machine, and for running it on real hardware.

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RE[5]: Comment by twitterfire
by DeepThought on Fri 24th Jan 2014 06:33 UTC in reply to "RE[4]: Comment by twitterfire"
DeepThought
Member since:
2010-07-17

What bugs me is that Intel & AMD haven't done the obvious and provided a simple and fast way to pass messages directly across a virtual memory boundary. Given the size of even an L1 cache in a modern CPU, why the heck can't I have some way to directly map a 4k page of that cache into one or more processes and use it as a ring buffer or FIFO?


I wonder, is the cache in x86 system tagged by the virtual address?
On PowerPC it is tagged by the physical address, though this is a problem on "normal" context switches, for MP it is "HW" support.

Regarding mapping a page, I'd say if you map the same virtual address in two processes, you can rely on the cache controller and you should have no performance loss, You copy your data into the page and it goes also into the cache.

Reply Parent Score: 2

RE[6]: Comment by twitterfire
by galvanash on Fri 24th Jan 2014 19:40 in reply to "RE[5]: Comment by twitterfire"
galvanash Member since:
2006-01-25

I wonder, is the cache in x86 system tagged by the virtual address?


Sandy Bridge at least, and AMD's bulldozer are virtually indexed and physically tagged (VIPT). Is suspect that this is probably the norm for all of the last few generation x86 chips from both Intel and AMD (have no idea about VIA).

It certainly isn't a requirement of the x86 ISA though, as the cache is architecturally hidden (you can pretty much do whatever you want, even no have a cache at all).

Many ARM designs are virtually indexed and virtually tagged (VIVT), which is probably the only other method still being employed in modern cpu caches. PIPT caches are more or less by definition too slow nowadays.

Its all about tradeoffs...

Reply Parent Score: 2

DeepThought Member since:
2010-07-17

THX,

I am not sure what "virtually indexed" means. I have to read this up.

Reply Parent Score: 1