Linked by Thom Holwerda on Mon 31st Mar 2014 21:35 UTC
Apple

AnandTech on Apple's A7 processor:

I suspect Apple has more tricks up its sleeve than that however. Swift and Cyclone were two tocks in a row by Intel's definition, a third in 3 years would be unusual but not impossible (Intel sort of committed to doing the same with Saltwell/Silvermont/Airmont in 2012 - 2014).

Looking at Cyclone makes one thing very clear: the rest of the players in the ultra mobile CPU space didn't aim high enough. I wonder what happens next round.

This is one area where Apple really took everyone by surprise recently. When people talk about Apple losing its taste for disruption, they usually disregard the things they do not understand - such as hardcore processor design.

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RE[2]: Comment by Drumhellar
by Drumhellar on Tue 1st Apr 2014 17:02 UTC in reply to "RE: Comment by Drumhellar"
Drumhellar
Member since:
2005-07-12

I always wondered why a 32 bit variant of x64 wasn't released with the same register advances, but without 64 bit capability. Perhaps that was benevolent forward thinking in case of x86, although it's hard to see a usecase for that in mobile. Ultimately I don't think that aspect really matters one way or another.


Well, the instruction format would have to be changed to accommodate extra registers - the x86 instruction format uses 3 bits to encode either source or destination register, which isn't to select from additional registers.

To make a 32-bit chip with the other architectural enhancements of 64-bit, you'd still have to enter a different processor mode - say, x86+, to execute software that takes advantage of the extra registers and flat x876/sse register file (x86 uses a stack), and executing older 32-bit code would still require a mode change.

IIRC, adding AMD64 capability to the Pentium 4 (Well, technically Intel-64, the purposely slightly incompatible knock-off) only increased the die space by ~5% anyways, and by the time x86 was being dropped into ultra-mobile designs, well, the 4GB address limitation was already looming close in those designs. A x86+ design would have probably only had one generation of use...

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