Linked by Thom Holwerda on Fri 28th Jul 2017 19:49 UTC
AMD

So far all the products launched with Zen have aimed at the upper echelons of the PC market, covering mainstream, enthusiasts and enterprise customers - areas with high average selling prices to which a significant number of column inches are written. But the volume segment, key for metrics such as market share, are in the entry level products. So far the AMD Zen core, and the octo-core Zeppelin silicon design, has been battling on the high-end. With Ryzen 3, it comes to play in the budget market.

AnandTech's review and benchmarks of the new low-end Ryzen 3 processors.

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RE[6]: Comment by raom
by Treza on Sat 29th Jul 2017 22:09 UTC in reply to "RE[5]: Comment by raom"
Treza
Member since:
2006-01-11

Then why is EVERY x86/x86-64 internally a RISC processor?


I'm getting tired of this nonsense.

There is no "internal RISC processor". There is microcode. Microinstructions do not make an instruction set, Intel CPUs used to execute micro-ops sequentially (8086...80386), now it is pipelined, out of order, speculative, ... but this do not make a RISC.

RISC/CISC is about instruction sets, and one of the ideas behind RISC was discarding the microcode and replacing it with a straightforward instruction decoder.

Reply Parent Score: 2

RE[7]: Comment by raom
by tylerdurden on Sat 29th Jul 2017 23:39 in reply to "RE[6]: Comment by raom"
tylerdurden Member since:
2009-03-17

I think part of the confusion also comes from the fact that originally there were many research teams working on RISC designs, and each team had a different defintion for what the term meant.

Some RISC projects were indeed about exposing both the microcode and pipeline thus passing the programming complexity on to the compiler. Ironically, most RISC designs originally were not intended to be programmed by hand...

Reply Parent Score: 2

RE[7]: Comment by raom
by Alfman on Sun 30th Jul 2017 00:33 in reply to "RE[6]: Comment by raom"
Alfman Member since:
2011-01-28

Treza,

I'm getting tired of this nonsense.

There is no "internal RISC processor". There is microcode. Microinstructions do not make an instruction set, Intel CPUs used to execute micro-ops sequentially (8086...80386), now it is pipelined, out of order, speculative, ... but this do not make a RISC.


The problem is that "RISC" is associated with different meanings, and whether we like it or not we now have to be more concise than just saying "RISC" and automatically expecting everyone to be on the same track. And before you disagree with me, I want you to take note that your own post used two of the differing meanings:

1) "RISC/CISC is about instruction sets"
and
2) "one of the ideas behind RISC was discarding the microcode and replacing it with a straightforward instruction decoder."

I'm personally not at all bothered by this, but some posters do become frustrated when "RISC" is associated with this idea of a simple implementation even though it's commonly used in that context. Many of the arguments in years past have started with semantic differences, so I'm hoping maybe we can all explicitly move beyond that and steer the discussion to something more substantive instead ;)

With that in mind, I found this paper on the topic quite interesting:
http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-s...

Edited 2017-07-30 00:33 UTC

Reply Parent Score: 2