Linked by Thom Holwerda on Wed 7th Dec 2005 09:41 UTC, submitted by Sebastian Schildt
Sun announced plans to publish specifications for the UltraSPARC-based chip, including the source of the design expressed in Verilog, a verification suite and simulation models, instruction set architecture specification (UltraSPARC Architecture 2005) and a Solaris OS port. The goal is to enable community members to build on proven technology at a markedly lower cost and to innovate freely. The source code will be released under an Open Source Initiative (OSI)-approved open source license. The 'older' SPARC architectures were also open.
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RE[6]: Verilog? (clock rates)
by nimble on Thu 8th Dec 2005 17:05
in reply to "RE[5]: Verilog? (clock rates)"
Member since:2005-07-06
Your comparing instruction latency of Sparc code with x86 code. This is completely pointless.
Kneejerk reaction. You have made no effort to understand the point I was making.
Instruction latencies are obviously no benchmark for overall processor speed, but were used here to compare the pipeline implementations.
Member since:
Woah, slow down there Apples != Oranges. Your comparing instruction latency of Sparc code with x86 code. This is completely pointless.
"Yeah, my 86' chevy citation is a superior piece of equipment to your Harley Davidson because I've got more tires than you."
1 Sparc Instruction != 1 x86 Instruction.
Sorry. Also, SPARC forces stuff like branch prediction in the assembly, so instruction latency is less of an issue, since your less likely to have to flush the pipe. Pickup a computer hardware 101 book.