Linked by Thom Holwerda on Tue 24th Jan 2006 16:58 UTC
Hardware, Embedded Systems Yesterday, we reported on an article about the demise of the Alpha. That article was the first part in a series about the future of processor design. Today, part II has been published: "In terms of the architecture itself, AMD's Athlon 64 platform, at the stage it is at right now, does not offer that much of a performance advantage, and AMD should not be resting on its laurels. This is because on the desktop, interconnects as such play less of a role. It's on servers and multi-processing systems that you can take advantage of scaling, and that's where interconnects such as HyperTransport have a role. But when you talk about a single-chip desktop system, whether it's one, two or four cores, the efficiency of the chipset still plays a very important role."
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RE: Arrogant Article
by renox on Wed 25th Jan 2006 06:34 UTC in reply to "Arrogant Article"
renox
Member since:
2005-07-06

I disagree: x86 is bad, and little crufty is understating: compare SSE vs Altivec for example.

From ease-of-use point of view: its use of low-endian makes hard to read hex dump of memory, low number of register, not-orthogonal ISA...

x86 instruction density can be matched by RISCs as ARM's Thumb2 have shown (Thumb had a performance impact, I don't know if it's still the case with Thumb2).

Now I must admit that I don't remember if the paper I've seen which compared instruction density was using also OO code for the comparison.

Reply Parent Score: 1

RE[2]: Arrogant Article
by nimble on Wed 25th Jan 2006 07:17 in reply to "RE: Arrogant Article"
nimble Member since:
2005-07-06

I disagree: x86 is bad, and little crufty is understating: compare SSE vs Altivec for example.

Both use 128-bit vectors, both support byte, short, int and float vectors. SSE also supports double vectors. The instruction sets are quite similar.

SSE has only 8 registers in comparison to Altivec's 32, but makes up for much of that that by being able to use powerful memory addressing in every instruction, not just load/store.

Where's your point?


x86 instruction density can be matched by RISCs as ARM's Thumb2 have shown

Yes, but should Thumb2 still be considered a RISC instruction set? It hasn't got fixed-size instructions, and it only has 8 general-purpose registers.

I think they should have sacrificed three-operand instructions rather than halve the number of registers compared to the full ARM instruction set, but it's still a good compromise between orthodox RISC and pragmatic CISC.

Reply Parent Score: 1

RE[3]: Arrogant Article
by renox on Wed 25th Jan 2006 16:41 in reply to "RE[2]: Arrogant Article"
renox Member since:
2005-07-06

> should Thumb2 still be considered a RISC instruction set?

-Load/Store architecture? Check.
-Fixed instruction size? No: but only two mode 16/32 bit compared to 8/16/24/32.. in tradionnal CISCs.
-Simple encoding? More or less, debatable as of course it's more complex that ISA with only one length.
-For the registers, even in thumb mode the 8 registers are fully orthogonal and there are 3 other register for instruction pointer,etc.

So it still looks mostly like a RISC, but RISC isn't a religion, the real questions are: is-it easy to use for human, compilers and does-it use transistors efficiently?
For the two first point I think that this is the case, for the third point I think that it still take less transistor to handle Thumb2 that to decode x86 but it's just a guess.

Reply Parent Score: 1

RE[2]: Arrogant Article
by edwdig on Wed 25th Jan 2006 08:36 in reply to "RE: Arrogant Article"
edwdig Member since:
2005-08-22

I disagree: x86 is bad, and little crufty is understating: compare SSE vs Altivec for example.

SSE wasn't that great, but SSE2 and SSE3 are pretty good. AltiVec seems to be slightly faster, but SSE3 is more flexible in both operations and datatypes.

From ease-of-use point of view: its use of low-endian makes hard to read hex dump of memory, low number of register, not-orthogonal ISA...

Big endian makes it easier to stare at a random memory dump and figure out what's going on. Little endian makes code simplier as it makes it simplier to do things like treating an int as a short or a char. It's not something you'd directly notice unless you program in assembly, but it does tend to result in smaller code.

x86 instruction density can be matched by RISCs as ARM's Thumb2 have shown (Thumb had a performance impact, I don't know if it's still the case with Thumb2).

I don't know anything about Thumb2, but Thumb certainly sucked. The only time it made any sense was if your hardware couldn't provide a 32 bit memory interface, and even then you were still better off using ARM for certain things.

Reply Parent Score: 1

RE[3]: Arrogant Article
by renox on Wed 25th Jan 2006 12:37 in reply to "RE[2]: Arrogant Article"
renox Member since:
2005-07-06

Does SSE3 has a multiply-accumulate operation?
I remember that it was missing in previous version.

Little endian simplifies some assembly language trick, big endian simplifies other assembly language trick, I'm not sure that there is really a benefit of little endian for the assembly language programming here, but human read in big endian and this is a big difference.

What do you say that Thumb sucked? Because of the performance impact?
Anyway I've not said Thumb but Thumb2 where you can mix 32 and 16 bit instructions.

Reply Parent Score: 1