Mainframes still play a vital role in today, providing extremely high uptime and low latency for financial transactions. Telum II is IBM’s latest mainframe processor, and is designed unlike any other server CPU. It only has eight cores, but runs them at a very high 5.5 GHz and feeds them with 360 MB of on-chip cache. IBM also includes a DPU for accelerating IO, along with an on-board AI accelerator. Telum II is implemented on Samsung’s leading edge 5 nm process node.
IBM’s presentation has already been covered by other outlets. Therefore I’ll focus on what I feel like is Telum (II)’s most interesting features. DRAM latency and bandwidth limitations often mean good caching is critical to performance, and IBM has a often deployed interesting caching solutions. Telum II is no exception, carrying forward a virtual L3 and virtual L4 strategy from prior IBM chips.
↫ Chester Lam at Chips and Cheese
If you’ve been keeping track, you can possibly deduce that I’m bit of a sucker for IBM’s mainframes and big POWER machines. These Telum II processors are absolutely wild.
Unpopular opinion: Machines like this are the last true supercomputers. Everything else is either a high-end PC or a bunch of PCs tied together with really high-speed LAN.
The super people would take offense you referring a mainframe as a super 😉 J/K
In any case, A computer is a computer is a computer. These use plenty of commodity stuff as well FWIW.
I visited the Z-series guys when I was @ TJ Watson. Really neat team, I thought it was very interesting how the put a lot of effort on mechanical failure analysis.
This sort of tech is just on another scale to most computers. 2.8GB virtual L4 cache. 380MB virtual L3 cache…. It’s practically unbelievable. And at latencies that make high end server cores look sluggish.
My first PC had 256MB RAM… I bet one of those cores could emulate my first PIII PC an order of magnitude faster, and all in cache to boot
These systems are extremely transaction-focused, and their per-thread performance is a bit behind x86/ARM. So it won’t make for a good x86 emulator 🙁
If you have the wallet for it, you can get over 1GB L3 cache per socket on x86 nowadays. So you can virtualize your original P3 PC entirely on cache at way-faster-than-native speed, without any translation/emulation penalty/overhead.
I think that’s the point though. Someone ran Linux on a 4004. Not because it was any good at it, but because they could.
Playing Doom or heck, even Crysis, on one of these Telum II’s would be such a power play. I don’t know what kind of graphical interface you could attach to a mainframe (if any), but it’d still be cool to see. You could run UNIX on a System/370 (https://gunkies.org/wiki/UNIX/370), so QEMU on a Telum is surely possible.
LOL. Nobody ran linux on a 4004.
Xanady Asem,
It’s not going to be efficient mind you, but Turing completeness means it’s possible.
https://arstechnica.com/gadgets/2024/09/hacker-boots-linux-on-intels-first-ever-cpu/
Like The123kingsaid: not because it was any good at it, but because they could.
As I said, nobody ran linux on a 4004.
FWIW that’s just using a 4004 to do some of the integer datapath control logic for a MIPS I HW emulator board. He could have used any random bitslice processor from the 70s.
He sort of rediscovered how early RISC CPUs were prototyped, or how some PDPs and VAXens were implemented.
Xanady Asem,
There is no MIPS hardware. Read the article again, here’s the detailed writeup:
https://dmitry.gr/?r=05.Projects&proj=35.%20Linux4004#_TOC_38895bf939f056cd960d0cc0e3b52be6
It’s physically running on a 4004. It’s emulating an architecture supported by linux. In principal a 4004 compiler could be written for linux too, but it’s just a funny project so the author is free to choose how to accomplish it.
I read the article, which is why I wrote what I did.
He just wrote the FSM’s for the control logic of a MIPS I integer pipeline in 4004 assembler. And implemented the architectural registers and a bunch of other state support and IO on that board. He then runs linux on top of that emulated MIPS, at Khz speeds, by piping MIPS instructions into it.
It’s basically an old school HW architecture emulator. A hilariously unintended waste of time rediscovering the wheel, but naming it something else.
Xanady Asem,
Please take a closer look.
If you just took a quick glance at the picture you might think special chips were used to offload MIPS operations like the section for “MIPS Registers” and “MIPS TLB”, However take a look at those part numbers, these are actually original intel parts that made up the MCS-4 back in the day.
https://en.wikipedia.org/wiki/Intel_4004
The author just happened to label the intel DRAM to indicate the MIPS functionality he was implementing on them, but they are original components and all the MIPS logic is done in the 4004. Unless your accusing the author of lying….is that what you think? If not, then yeah it seems pretty legit.
LOL. No I am not accusing the author of lying. Nice try though.
Xanady Asem,
So we’re in agreement that he did what he said he did? Well then I’m glad we can end on an agreement.
You shot.
You missed.
Again…
Xanady Asem,
What are you even talking about? You haven’t articulated a specific source of disagreement. You just seem bent to do so.
I already wrote plenty about this, twice. Simply expanding on how linux was being run in that HW emulator, which happens to use a 4004 as its controller.
Keep digging w whatever nonsense you have to resort to have anything to say in discussions that are clearly outside of your paygrade (academically and professionally).
LOL
Xanady Asem,
It’s a purely software emulator. As the author said there is only a 4004 CPU. Linux is genuinely running on a 4004. Of course it’s too slow to be useful, but it’s technically working. Whatever your problem is with his work, I’d say the bragging rights of running linux on a 4004 were earned, he’s got the schematics, video, and everything.