Linked by Thom Holwerda on Thu 7th Jul 2005 19:16 UTC
IBM has today presented various new versions of their G5 processor at the Power Everywhere Forum in Japan. Firstly, it introduced the much-anticipated PowerPC 970MP, the dual-core version of the G5. In addition, they also announced 3 low-power G5s, ranging from 1.2Ghz at 13W to 1.6Ghz at 16W. These processors will most likely find their way into Apple's Macs.
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RE[5]: Too little, too late
by nimble on Fri 8th Jul 2005 06:55
in reply to "RE[4]: Too little, too late"
Member since:2005-07-06
having dedicated L2 caches has some advantages, in that it allows greater bandwidth per processor,
Depends on whether the shared caches haven't got a wider bus. Does anyone know?
It also depends on whether those buses are anywhere near fully utilised.
and easier scalability to quad core configurations.
Why? It just moves the work of integrating more cores to the other side of the cache.
It also has some disadvantages, namely more cacheline ping-ponging when both processors are working on the same data.
Plus the fact that 1 MB of cache goes unused when there's only one thread or when one of the threads doesn't need much L2 cache.
News
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PocketNow interviews Marc Dillon, and there's an interesting note about why Jolla is keeping the display properties under wraps: "We're leaving some of those details out because we do understand that there are a lot of really big players in the market and they tend to take certain components in the market and dominate them. We created the ability to actually be able to run Sailfish on multiple hardware displays and be able to swap components, so this is part of the demand and supply planning phase. We are committed to this industrial design which is a 4.5-inch display, an 8 megapixel camera on the back and a front-facing camera at the front, and the exact specs of the display we'll provide when we're close to delivery." Something you rarely hear anything about.
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Member since:
2005-07-06
Actually, the current dual-core processors from AMD give each processor a dedicated L2, and allow them to communicate at high-speed over the on-chip SRQ (system request queue). Having dedicated L2 caches has some advantages, in that it allows greater bandwidth per processor, and easier scalability to quad core configurations. It also has some disadvantages, namely more cacheline ping-ponging when both processors are working on the same data.