Linked by Thom Holwerda on Thu 18th Aug 2005 16:46 UTC, submitted by Nicholas Blachford
Intel "At next week's Intel developer forum, the firm is due to announce a next generation x86 processor core. The current speculation is this new core is going too be based on one of the existing Pentium M cores. I think it's going to be something completely different."
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latency is the issue
by on Thu 18th Aug 2005 18:30 UTC

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Almost everything about processor design that creates large scale power has to do with latency avoidance at all possible costs. When you throw that out the window and realize that massively pervasive threading can hide most latencies then processors can be become pretty simple again and can be had for pennies a pop (even a 486 like core at 1GHz).

Over the last 15yrs Pentiums have gotten only about 30x faster (Toms Hardware P100 to P4) and have used a clock that is also 30x faster, but the DRAM memory wall has barely moved (maybe 100ns to 60ns RAS cycles). The logic, transister cost though went up by maybe 100 fold just to get the clock to Mips performance to scale. This is very bad engineering.

Imaging building a suspension bridge that went 10x the distance but used 100x more steel to do the job.

By having 16 cpus each running 4x slower, (say 1000Mip each), the memory wall falls down to more manageable levels. One could go much further, several companies already can pack several hundred simple cpus onto a single chip but then memory bandwidth in/out of chip becomes the killer. Even a high end FPGA can pack >100 small cpus but only at 150Mips each sigh.

The real way to move forward is to thread the memory system too so that DRAM can issue new memory requests at rates far closer to cpus clock rates. Micron has RLDRAM which does new cycles every 2.5ns and has latency of 8 clocks (20ns). Hide those clocks with 8 way threaded cpus and the DRAM now looks like only a few times slower than cpu again. Now it takes alot more than just that to make a big jump forward.

As long as single threaded PCs use conventional almost single threaded 60ns DRAM, they are going to burn watts.

transputer guy

Reply Score: 5

RE: latency is the issue
by Ronald Vos on Thu 18th Aug 2005 19:13 in reply to "latency is the issue"
Ronald Vos Member since:
2005-07-06

Thanks for the info, tg.

For the rest: remember this article is speculation. But it does describe a way to move away from x86's hindrances while maintaining compatibility. I'm just not sure how anyone wants to implement 'translating binaries and then saving them' on modern day's more security-paranoid/aware OSes. I'm not sure users apreciate their files being modified without their awareness, especially developpers developping cross-platform.

Reply Parent Score: 1

RE[2]: latency is the issue
by on Thu 18th Aug 2005 19:26 in reply to "RE: latency is the issue"
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As far as I can remember, x86 has only been a frontend since the original Pentium was released.

And I blame AMD for prolonging the life of the x86 ISA, by going the "simple" route and spit out their Opteron and derivative CPU's.

It has long been my belief that Intel originally didn't want to extend x86 to 64bit, but instead start over with a new ISA that is better optimized and more futureproof, when the time for that was good.

Reply Parent Score: 1