Linked by Thom Holwerda on Sat 7th Nov 2009 14:33 UTC, submitted by J!NX
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dude, processors have been using tagged TLBs (as well as other TLB managing techniques) for eons. Heck, I think the MIPS R4000 had it in silicon almost 2 decades ago. Commercial AMD64 procs have been using tagged TLB designs for a while too.
Many processor architectures such as MIPS have had tagged TLBs for a long time, but x86 has not. Intel and AMD have only recently started introducing tagged TLBs, any they are not fully used yet.
I think Xen and whatnot have been using/expecting tagged TLBs for a while now.
AMD64 has had tagged TLB literally from the get go. Pacifica and whatever it is Intel names their hypervisor technology have been around for a while too and expanded on that. I think you may be referring to things like nested page tables and such.
Further, x86 allowed for software management of certain TLB functions, as to make a more informed request for a TLB flush.






Member since:
2009-03-17
dude, processors have been using tagged TLBs (as well as other TLB managing techniques) for eons. Heck, I think the MIPS R4000 had it in silicon almost 2 decades ago. Commercial AMD64 procs have been using tagged TLB designs for a while too.
Furthermore, microkernels are not necessarily that bad when it comes to context switch issues (in fact context switch overhead hasn't been an issue for the better part of the past decade at least due to the sheer difference between the quantum timer tick of modern processors and its pipeline clock, as well as things like out-of-order etc. Also, most of the servers in the microkernel are in the same privilege ring and don't have to necessarily trigger a compound context switch.
A lot of people criticise X86, but it is funny how the baroque protection and privilege mechanisms, ended up being quite beneficial for kernel operation.