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CISC and RISC, and even VLIW, have been meaningless acronyms ever since microarchitecture and ISA became decoupled concepts a while ago.
The average x86_64 CPU tends to a very modern microarchitecture who happens to be able to execute old x86 instructions. Same can be said about SPARC, and POWER for example. Not one of those architectures happen to execute most (if any at all) of their ISA's natively. All of them break them down into micro ops which are not visible to the programmer.
SPARC and POWER, for example, had to do some serious architectural gymnastics in order to allow aggressive superscalar, vector, and out-of-order execution of their original ISAs. Just as intel and AMD has to do with x86.
The main advantage most RISC CPUs had over old CISC designs, in the desktop/high performance areas, was that they offered a cleaner path to 64-bits and marginally faster pipelines... when transistor budgets for logic were still an issue. But that was almost 20 years ago.
Edited 2011-09-20 23:16 UTC
Well they still are in most (units shipped) processors, where low power usage matters; like in ARM, still quite RISCy, and at least some time ago still not very microcoded.
Edited 2011-09-27 00:15 UTC




Member since:
2005-07-11
There are also very few true CISC processors left. The complex instructions are programmed in microcode running on a very simple instruction set implemented in hardware. You could almost say that RISC and CISC sort of converge towards each other to a more optimal golden middle, but not quite. There are still differences between the two, such as special purpose vs general purpose registers, address modes, etc.