During his keynote address at San Francisco's Moscone Center, Otellini unveiled the company's next-generation, power-optimized micro-architecture for future digital home, enterprise, mobile, and emerging market platforms aimed at a new category of converged consumer devices.
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Member since:2005-06-30
The cores do share the same memory controller, but the K8 isn't particularly bandwidth constrained and it's a side-effect of sharing a memory controller rather than moving the memory controller on-die. The K8's multicore strategy is better than the P4's. Benchmarks run with variable increases in the memory bandwidth typically result in fairly modest performance gains, and the discussion as far as games is concerned is a tad fishy because PC game engines are not typically multithreaded with kernel threads, though there are a few that make use of coroutines and some that make limited use of multiple threads.
Member since:2005-07-06
I call Fudulent statement.
Now prove me wrong.
I wish people would stop calling things "FUD" which are not. I was not posting "fear, uncertainty, and doubt". Even if I was posting something incorrect, which I do not believe I was, it would be an "incorrect statement", not "FUD".
See this diagram as proof:
http://images.anandtech.com/reviews/cpu/amd/athlon64x2/preview/AMDa...
As you can see a dual-core setup for the Athlon64-x2 shares one memory controller.
Now, this is not the case for SMP systems, just dual core.
Yes, I realise that Intel's dual-core chips will be sharing a single memory controller on the motherboard. However, each processor has a full amount of bandwidth to communicate with the memory controller instead of sharing a single path. That makes some difference.
Member since:Yes, I realise that Intel's dual-core chips will be sharing a single memory controller on the motherboard. However, each processor has a full amount of bandwidth to communicate with the memory controller instead of sharing a single path. That makes some difference.
How so? This is not a sarcastic or rethorical question, mind you... an honest request for explanation from someone who is not into CPU design at all.
In a naive point of view, a bandwidth bottleneck is a bandwidth bottleneck, whether it happens on die or on motherboard. Two threads running on different cores will need in both case to reach through the memory controller all along the path the ram for their work, in both cases sharing the bandwidth. Again, from my naive point of view, the lower latency of an on-die memory controller actually reacts 'faster' to changes in bandwidth occupation thus optimizing the flow? I don't really know 
Please explain.
Member since:
but they also have a disadvantage in that both processors have to share 6.4gb/s of potential memory bandwidth, whereas Intel since they do not have an on-die memory controller can have each CPU use the full potential bandwidth.
I call Fudulent statement.
Now prove me wrong.