Star Intel Research Papers on Programmable Multicore Architectures
Linked by Thom Holwerda on Thu 16th Aug 2007 17:24 UTC, submitted by burnttoy
Intel Intel on Tuesday said it would release this week eight technical papers describing key findings from the company's work on future programmable multicore architectures. The papers will be published in the Intel Technical Journal and will provide details on how the company expects future microprocessors with simplified parallel programming models to evolve.
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RE[4]: Tired of pre-announcements
by jmcp on Fri 17th Aug 2007 01:27 UTC in reply to "RE[3]: Tired of pre-announcements"
jmcp
Member since:
2006-08-06

As I understand it, a lot of work is being done in the compiler and the underlying OS to make HTM support *transparent* to the application and userbase.

This isn't something that's just been thought of recently, it's been in the works (skunkworks, of course!) for years

http://scholar.google.com/scholar?hl=en&lr=&q=hybrid+transactional+...

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Wes Felter Member since:
2005-11-15

As I understand it, a lot of work is being done in the compiler and the underlying OS to make HTM support *transparent* to the application and userbase.

But AFAIK apps will still have to have begin_transaction() and end_transaction() in the code. Transactional memory makes multithreaded programming easier, but it doesn't create the threads for you.

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tuttle Member since:
2006-03-01

But AFAIK apps will still have to have begin_transaction() and end_transaction() in the code. Transactional memory makes multithreaded programming easier, but it doesn't create the threads for you.


Pure functional languages are very easy to parallelize. So if you want a language where you do not have to explicitly define threads, any functional language such as ocaml, clean or haskell will do just fine.

But in this case "transparent" just means that the transaction implementation will switch seamlessly from fast hardware transactions to software transactions when the transaction gets too big for the hardware cache. So the developer does not have to be aware of the limitations of the hardware transactional memory implementation.

Edited 2007-08-17 19:19

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