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Going out on a limb... The MS R&D guy's status:

"Robert Morgan is working to get IA-128 working backwards with full binary compatibility on the existing IA-64 instructions in the hardware simulation to work for Windows 8 and definitely Windows 9."

He specifically says "IA-64". Within Microsoft and by almost everyone else, 64-bit x86 is generally referred to as x86-64, x64, or even AMD-64 (as a nod to the original designer of the specification). If you were talking about Intel x86, you would generally use the term Intel 64 or EM64. "IA-64", however, specifically refers to Itanium - that is the original name given to the ISA by Intel.

So if this guy is using his terms correctly, he is talking about Itanium when he says IA-64. If that is true, then when he says IA-128 he MUST also be talking about Itanium, or the talk of backwards compatibility makes little sense.

Unlike x86, extending Itanium to 128-bit is a lot more straight forward, and since it is targeted only at the very high end of computing it might actually make some sense.

64-bits of physical memory is not limiting in most senses. But having a full 128-bit segmented virtual address space would allow you to write a hypervisor for running 64-bit VMs that would:

1. Require no changes to the 64-bit ISA - Each 64-bit VM would see memory in exactly the same way as before, they simple wouldn't know about the segment offsets.
2. Let the hypervisor manage memory very, very efficiently. Each VM would simply be assigned an offset address, and the VM would get a full 64 bit address space that is directly mappable into the hypervisors 128-bit memory space.
3. If the hypervisor was implemented to use a 128-bit file system for storage of the VM images, it would allow it to memory map the images directly, no funky stuff required.
4. If ONLY the hypervisor used 128-bit mode, you may not need to do much if anything to the existing computational units. Simply adding an additional 128-bit ADDR (or adding a 128-bit "mode" to the existing ADDR) or an additional address calculation unit might be enough to implement this, since the scope of work for a hypervisor is limited primarily to memory management tasks.
5. 128-bit of virtual address space is simply HUGE. Huge enough that security can be implemented simply by randomizing segment assignments (there would be a 16TB address space JUST for the 64-bit segment addresses). Having that much space would allow for a very simple and secure memory model.

This makes much more sense to me than anything else. The mention of high security fits, and Windows is still one of the more popular choices of OS for Itanium. MS already has shown interest in hypervisors for their OS - making a version of Windows that takes advantage of these (admittedly conjectured) extensions to the Itanium ISA would give MS a competitive advantage in the high end computing space, something they have been desperately trying to get a foot hold in for years now.

Granted, this is pretty out there - but if there is any truth to what that guy posted it is probably closer to this than anything else. The 128-bit FPU thing could fit too, but I'm stuck on his use of the term "IA-64"...