Linked by Thom Holwerda on Thu 26th Aug 2010 23:24 UTC
IBM At the Hot Chips 2010 conference, IBM announced their upcoming z196 CPU, which is really, really fast. How fast? Fastest chip in the world fast. Intended for Z-series mainframe computers, the Z196 has a clock speed of 5.2GHz. Measuring just 512 square millimeters, the Z196 is fabricated on 45nm PD SOI technology, and on its surface contains almost one and a half billion transistors. My... Processor is bigger than yours.
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tylerdurden
Member since:
2009-03-17

Why would I need to read a 3rd party article, by a non-technical writer, when I was getting the specs directly from IBM?


Do you guys even comprehend the impossibility of a single chip at that 45nm process with those cache sizes?

See the specs from IBM directly, or if you need a 3rd party check wikipedia:

http://en.wikipedia.org/wiki/IBM_z196_(microprocessor)

A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.

Reply Parent Score: 3

gilboa Member since:
2005-07-06

A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.


Actually, the biggest issue with large L1 is not flush-on-context switch.
The bigger the cache the bigger the index tables (assuming that they are not using direct mapped cache), which in turn, increases the latency.
As a result, L1 caches tend to small and extremely fast, with bigger and slower down the pipeline until you reach the main relatively slow main memory.

- Gilboa

Reply Parent Score: 2

tylerdurden Member since:
2009-03-17

You are correct, I was just giving an example as to why really large L1 caches are not only useless but become problematic, touching on the fact that these cores are used in SMT in which case context in the L1s actually has an effect.

Reply Parent Score: 2

JAlexoid Member since:
2009-05-19

Why would I need to read a 3rd party article, by a non-technical writer, when I was getting the specs directly from IBM?


Do you guys even comprehend the impossibility of a single chip at that 45nm process with those cache sizes?

See the specs from IBM directly, or if you need a 3rd party check wikipedia:

http://en.wikipedia.org/wiki/IBM_z196_(microprocessor)

A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.


First of all, remember that Mainframes are designed to push I/O ops at unparalleled speeds. Their main focus forever was I/O performance, not processing speeds. That is why mainframe processors are not used in their super-computers, they are just not designed for raw calculations. Add to that, these machines are bundled with with some fast storage units - and you get ultra low wait times for data.
I've actually seen how these machines perform, Oracle RAC isn't a contender when comparing the I/O heavy DB operation performance these machines can achieve with DB2.

Reply Parent Score: 2

tylerdurden Member since:
2009-03-17

And that has what to do exactly with the post regarding the fact that the previous posters reported the wrong size of caches?

Reply Parent Score: 2