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viton,
"You're doing over-engineering here. Branch elimination could be helpful, but it will work fine without it."
That's because your aiming for lower branches than I am.
"ARM need more registers to implement load-op and op-in-memory x86 instructions. 16 registers is not much."
What your talking about isn't going to run as well as something optimized to use the ARM's registers natively. The x86 register limitation is a well documented bottleneck even on x86 itself where intel and amd have spent billions on making it perform well. It perplexes me why you think an ARM processor could run x86 code as well as intel can.
"Qemu is a full-system emulator. x86 on WinRT should not mess with MMU pages."
Yes, qemu manages the MMU, but even when everything is loaded into memory and running will have to incur overhead as a results of implementing x86 semantics & registers on a foreign architecture.
"The only I see here is a lack of understating of ARM arch and binary translation."
So everyone else is wrong, enlightening that.
The goal, to my understanding, is to execute legacy programs with competitive performance, not a Guinness records for the sake of it.
I didn't made such a performance claims. I'm talking about good enough performance. Even if it is just 50%.
As I said, Intel engineers did ARM binary translation without any "magic buzz" about it. It just works.





Member since:
2005-08-09
You're doing over-engineering here. Branch elimination could be helpful, but it will work fine without it.
ARM need more registers to implement load-op and op-in-memory x86 instructions. 16 registers is not much.
there is no need to "time share" registers, so OOO is inherently going to work differently there.
ARM OoO is much more limited, but it has 40 rename registers (on cortex-A9)
Qemu already does what your talking about.
Qemu is a full-system emulator.
x86 on WinRT should not mess with MMU pages.
The only I see here is a lack of understating of ARM arch and binary translation.