Recent research on reconfigurable hardware designs has highlighted novel ways in which computers can dynamically change their structure to increase performance and density. However, work has only just begun to develop operating systems that can exploit theses types of hardware. Akin to hitting a moving target, making stable operating systems that can adapt to rapidly changing hardware will be an interesting challenge to operating systems researchers.
Reconfiguring Operating Systems
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Eugenia Loli
Ex-programmer, ex-editor in chief at OSNews.com, now a visual artist/filmmaker.
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I’m the only one who appreciates this post …
Thats Eugenia
i do as well, you saw it before me ;}
this type of tech presents an interesting challenge
I think that the level of abstration needed to support such a thing at the OS level requires a microkernel. That’s the only way to keep everything clear. It’ll be interesting to see how or _if_ something like Linux could adapt to a system like this.
I have been following the progress of this company http://www.starbridgesystems.com for a while. I believe this is what they are doing, and claim to have some impressive performance and high profile clients (like NASA). Does anyone know anymore about this? Aparently using their VIVA software you emulate many platforms and allow existing OSes like Un*x and Windows…
I’m preparing for a seminar about reconfigurable systems and had to pick one existing implementation to talk about.
Instead, I’m now going to talk about operating systems for reconfigurable systems.
Great timing, thanks
I found strange thet this post did not cause many comments. This is a very interseting technology and I hope we will see it in a few years in mainstream processors. Thanks for the link…
I remember reading an article about 4 or 5 years ago on something similar. It was about 2 guys contracted by the Navy to develope an alternative to current processor design. I think the article was in a NASA magazine I used to get.
They also used FPGA. As I recall their array constisted of 1,000,000 connections, it was connected to an Apple to load the software and was blazingly fast.
Last I ever heard about it till now.
Cool stuff. I hope they contiue the work.
The world of HW & SW are mostly orthoganal, very few people work in both domains comfortably. Embedded guys do it but still they keep the two side separate, ie choose a low level cpu ie 8051 & code it in C/asm with some small OS kernal.
What RC (Reconfigurable Computing) is really all about is the idea that a widget can be realised as both SW (say using C..) or HW (say using Verilog/VHDL/C/HandelC..) etc and that the widget is equally at home in SW or HW. Now the SW version can be executed on just about any computer and runs at some speed. The HW version runs on an FPGA & hence is limited to certain HW platforms but can run essentially 1-1M x faster. If the HW is an ASIC, it is no longer RC.
DSPs are esp good examples of this, the classic win modem is what most people use in pc, here the pc is executing the SW version of the widget, it is essentially a simulation of the HW widget. In this case the simulation is so optimised that any pentium is not too burdened by it & the speed is acceptable. The HW modem also exists in simulation at the ASIC house but it runs much more slowly than the same function win model since it is intended to show lots of detail and is never ever released to end user.
Imagine though a win cable modem. Since cable modem has 100x more data throughput, it will need 100x more SW speed to simulate it and that is beyond even a P4. Hence every cable modem I have seen is still packed with many DSP chips.
When I sit down & design a chip, I have a simulation of it running on my pc (usually in C) as well as finally an ASIC in hand. The ASIC takes 3 months & $Ms to fab from the Verilog source files, but I can also prototype it to an FPGA. FPGAs typically run 5..10x slower than ASICs but I can have a new proto in secs ..hrs & the costs can be a few $K hence the interest. I could even sell the C code as an app, and the packaged FPGA bit file as the 1000x faster HW version of it. Most ASIC guys don’t do this, they just sell final ASIC, the C/Verilog sources stay in the safe. It would need a new business model to sell both SW, FW (firmware for FPGA), HW versions of the same widget. Currently this business only exists between ASIC companies for widget parts or Intelectual Property (IP), ie USB, FireWire, SCSI, NIC blocks.
Now imagine something much more interesting, protein folding engine or a google search engine. These are mostly built in SW & run distributed over many slow PCs either end users or on farms. If the problem can be described in C it can be executed on a PC, BUT it can sometimes also be synthesized into HW and run on FPGA board. The total costs are similar, FPGA boards are curently quite expensive, $200..$50K but 1 PC with FPGA upgrade can then replace a small farm of PCs.
Now its unlikely anyone would ever ASIC a protein folding engine since these are more research projects & the code might be changed too often, but this is ideal for FPGA systems. If you were the NSA, you could FPGA your cryto systems & still have the option to ASIC it as well as just run the C code on the infinity farm.
Now have FPGAs & cpus collided yet on same chip. Yes Xilinx has 1-4 PowerPCs on their top of the line Virtex Pros with equivalent of 100K..1M+ gate equiv on top. Imagine you could build your own custom ppc Mac with all that FPGA on board. Problem is that the cpu cores only run at 300Mhz but the real power is in the FPGA side.
Also Altera has an Arm on board their top arrays but they have humbler ambitions.
So far there is no x86 with FPGA but Xilinx & Altera & AMD do have the Hyper Transport bus, so it may be possible to get an FPGA with HT port to sit on the bus as a coprocessor for a Hammer system.
I believe eventually Intel,AMD,IBM will get it that it may be time to offer RC capability to every user by putting it on cpu chip or at least nearby on mobo. Who would benefit from this? Well Adobe Photoshop could have all it’s filter DSP done in SW & or FW in a fat exe. I could do my ASIc design modelling as both SW and FW.
See comp.sys.fpga & google reconfigurable computing
I could go on & on &
You’d think that the current popular target for Software -> FPGA -> ASIC would be cryptography and its similar ilk.
My favorite store about reconfigurable hardware, though, is a friend of mine is doing some work for a company that sells an arcage machine that runs several different “Classic” arcade games (like Pac Man and Defender).
They licensed the ROMs from the original producers, but they “download” the video game motherboards into an FPGA to actually run the game. So, they’re not running something like MAME, rather they’re running “actual hardware”. It makes for a very compact and elegant design.
But the real interesting point of this all is it’s getting easier and easier to “throw hardware at a software problem”.
“But the real interesting point of this all is it’s getting easier and easier to “throw hardware at a software problem”.
Precisely! But then who said it was a SW problem to begin with, its just a lot easier to do SW solution first.
Um, RC game machine, hardly what I expected, but believable.
I just wish more of the SW types understood that quite a bit of HW & SW are interchangeable. At least in the HW world designers always spec performance even down to precise clock cycles counts & ns. SW instead comes with a EULA & a “don’t bother us if its broke” warning.
Oh well
This will only take off in environments where sharp HW & SW engineers are working closely together on problems with no limits on creativity.