How Genode came to the RISC-V CPU architecture

Submitted by cbass 2016-03-22 OS News 2 Comments

As a follow-up to Genode’s 16.02 release, the project just published an in-depth article describing the experience with the RISC-V architecture and the steps taken to enable Genode on this platform.

The article is targeted at enthusiasts interested in the practical use of RISC-V and can also be used as a guideline on how to bring Genode to a different CPU architecture.

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Thom Holwerda

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2 Comments

2016-03-23 2:22 am

Pro-Competition
This was/is a very useful project, not just to prove and refine the Genode porting process, but apparently they are exercising the RISC-V platform in ways that others may not be. I hope the RISC-V maintainers are listening to the feedback from the Genode team, and make adjustments as necessary.

It is interesting to see how the RISC-V ISAs are still in flux, but it seems to be getting close to stable. I can’t wait for real hardware!
2016-03-23 2:38 am

Alfman verbose=1
Because of the current lack of devices, for example no user-level timer, no input devices, and no framebuffer, we stopped short on building more sophisticated scenarios while also postponing libc support because it would not bring a tangible benefit at this stage.