Intel has confirmed that its ‘Prescott’ processor features a longer instruction pipeline than the current desktop Pentium 4. The announcement lends weight to media claims that the chip will run more slowly than its predecessor. In the meantime, you can see why Apple waited for the 90nm version of the PowerPC 970 before launching a G5-based Xserve 1U rackmount server: the latter’s heat dissipation characteristics.
Intel P4, IBM Power CPU News
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Mod me down after correcting this:
“…features a long instruction pipeline than the current desktop Pentium 4.”
That should be longer.
I wonder when G5 desktops will be coming out on the 90nm version, assuming they are not already. That should allow the G5 to be even quieter.
Halving the power consumption while increasing the clock is impressive IMHO. It also makes a Laptop G5 more feasible, though it would still have to be a tank.
That’s what I get for not reading the entire article (the 970FX is the laptop chip…)
wasn’t a while ago here at osnews an article about cisc vs. rics, and that intel (and maybe amd) will hit a heatdissipation-wall with their current designs in the not-too-distant future?
if so, will optimized x86-processors for low clockspeeds like the centrino and multicore-processors be a way out of the dilemma, or will intel be forced to go the risc-route?
Intel has already dumped cisc. The P4 is the last x86 based processor from Intel and they are planing to drop it in 2010.
I2 is a risc based chip. The current risc chips allow the processor to reorder the instructions based on aviable resources; the I2 is different in that it doesn’t do instruction reordering. The I2 expects the compiler to reorder the instructions into a 3 instruction group which the I2 will run as is; this moves a lot of the complexity from the processor to the compiler. Currently the compilers can’t do as good of a job as the hardware. Also, the design states a 3 instruction group; thus the processor can’t be made faster by adding another execution path (it could, but you would have to change the compiler and recompile all programs).
Multi-core wont help with the heat problem. Each core would generate the same amount of heat; it would also just make things worse since, the heat would now be in the same package. The big advantage of multi-core is that you can place multiple CPUs in a smaller package saving
AMD has a better chance of success then Intel. AMD shares chip process with IBM and can thus use IBM’s technology. Also, AMD is more interested in keeping the tempature down and the through put up; thus, their designs can do more then Intel’s at the same clock speed. This can been seen in the 2.2GHz Optron which is faster then Intel’s 3.0GHz P4.
More clock cycles, more stalls, and less performance per watt of power used.
While the P4 still uses the x86 (cisc) ISA it has a rather risc-like core. x86 instructions are internally decoded and translated into (several) micro-ops which are then executed by the core, so you can’t really call the P4 a cisc cpu. Of course the P4 needs a lot of hardware to do this translation and decoding, so Intel certainly is looking forward to finally leave x86 (IA32) and switch to IA64 (used in the Itanium).
The Register talks about a 30 stage pipeline, it will be really interesting to see how Intel manages to keep the pipeline filled and how they avoid stalls, though the P4 seems to perform quite well with its allready quit deep pipeline of 20 stages. Hyperthreading/smt certainly helps in this area, as does the trace cache…
>>This can been seen in the 2.2GHz Optron which is faster then Intel’s 3.0GHz P4.
This is probably due to different pipeline depths, the P4’s being deeper means that an instruction goes through more (smaller) steps, which can each be accomplished in shorter time, hence the difference in clock speeds.
Does anyone know if the Centrino <> P4 speed difference comes from different pipeline depths?
If by “I2” you mean “Itanium 2” then you are wrong. The Itanium is not RISC but EPIC (Expliciltly Parallel Instruction Code?). It is an evolution from RISC but not RISC itself. There is a good article on all this somewhere on arstechnica.com
If by “I2” you mean “Itanium 2” then you are wrong. The Itanium is not RISC but EPIC (Expliciltly Parallel Instruction Code?). It is an evolution from RISC but not RISC itself. There is a good article on all this somewhere on arstechnica.com
True, one could actually call it RRRRISC, Really, Really, Really Reduced Instruction Chip. EPIC is RISC to the extreme.
Regarding it becoming a standard by 2010. It will neer occur. Intel has done nothing to lay the ground the ground work for future ISVs. If they were truely interested they would started a move into the technical workstation/general workstation market by now, stayed there for a few years then dragged the chip down to the desktop by around 2009.