Intel Corp. chief technologist Pat Gelsinger showed off the company’s first reconfigurable silicon at the Intel Developer Forum this morning, together with a yet another way to improve the efficiency of the company’s general-purpose microprocessors.
Intel Shows Off “Helper Threading”, Reconfigurable Logic
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Stanford is doing a research project on Helper threads this summer, for which I am applying as a programmer. It seems that helper threads will lead to significant speed increases in the near future.
But I think I’ve seen this technology before. I just can’t place it.
Innovations are coming from increased “hardware assistance” to low levels of the operating system: either
(a) concurrency support (i.e. multiple CPU’s on the one die, hyper-threading, or hardware assisted concurrency); or
(b) specialisation support (i.e. network / graphic / crypto / etc engines either in separate chips, or in the die itself as ASIC [unlikely] or as an intermediate virtual machine language – e.g. like transmetas emulation of native processors, or JVM’s bytecode).
…but maybe someone here cares to enlighten me: does AMD have a strategy to help threads execute faster – like feeding data somehow to the idle parts of the cpu? I know they are using hypertransport already, but what about trying to get something similar to Intel’s hyperthreading?
This isn’t Intels first use of this technology, it’s said to have been used in their CPUs for many years now.
As for the Phone, interesting use of the tech but it completely ignores the one Phone’s biggest problem – battery life.
Reconfigurable logic generally takes quite a bit more power than dedicated silicon. I don’t think Ericsson or Nokia have anything to worry about…
Looks more like this tech will end up in Laptops, mostly in the US where they have umpteen different phone standards.
…but maybe someone here cares to enlighten me: does AMD have a strategy to help threads execute faster – like feeding data somehow to the idle parts of the cpu? I know they are using hypertransport already, but what about trying to get something similar to Intel’s hyperthreading?
AMD has decided to take the other route and in 2005 apparently they’re going to release a multi-core Opteron. By that time, the die size should have shrunk to the point where a mult-core Opteron should work out roughly the same price as a single one.
The fact is, hyperthreading in some cases actually provides WORSE performance than what we are traditionally used to. Maybe AMD weighed up the pro’s and con’s then decided that the performance increase would be greater and R&D cost lower of they simply made a multi-core design.
HyperThreading or multithreading was invented way before Intel floundered on it. Inmos was the 1st to sell significant nos of cpus that once dominated 32b cpu market (back when PCs were mostly 16b 386s etc) that had the par threading model in HW, it was called a Transputer.
Inmos even got most of it right in that par threads must syncronize with each other to work together on sub parts of a problem, eliminating unnatural sequentiality when it wasn’t neccesary.
x86.. whether 2 or 4 way threaded will never work properly as long as Intel continues to “not get it”. This means learning to write in par languages with a thread safe model that can be provably correct such as Occam-CSP or their derivatives or any HW language. It also means that process creation, communication, context swapping must be very light and fast, in the order of <20 cycles and that make its unfeasible with cpus that have or want to have large register sets.
Cpus that are fast for sequential computing are inherently slow for par SW and vice versa. To trully support par computing really requires having the reg set in memory and using reg caching HW to bring it to datapath. This allows 0 cycle context swaps and having many contexts live and ready to go on the fly as soon as another process is about to stall.
Intel could just go and read up on Transputers, & build a really modern design that would also run at 3Ghz but would also be scaleable to many cpus with message passing. If they don’t someone else surely will.
The last part about reconfigurable logic is a bit dissapointing, I would like to see it available on cpu so that developers can enhance the cpu with new temporary HW accelerateors but the P4 3GHz x86 model makes no sence since FPGAs really max out at about 300MHz. On the other hand a cpu built in FPGA can already be customised with coprocessors or new opcodes by those able to do HW-SW-cpu design.
RAW: Reconfigurable Architecture Workstation. An MIT project. This is what I was thinking of when I first read this article.
http://www.computer.org/intelligent/ex2000/pdf/x3002.pdf
http://slashdot.org/articles/99/07/26/0238235.shtml