“Itanium–you’ve gotta start somewhere”. ExtremeTech will take you from the genesis of IA-64 through the present day of Itanium, to the future: McKinley, Madison, and Deerfield. Then on to Hammer, PowerPC, SPARC, and more.
“It’s Nothing Like a Pentium“: Ten years in development, 325 million transistors and counting. “The Good Stuff: the Instruction Set” 41-bit VLIW instructions are elegant… until they get weird. “But What About x86 Compatibility?” It’s there, sorta. It probably won’t be the most popular feature. Read the first article of a three-part series at ExtremeTech.
Stack machines would appear to have been a thing of the past. However the first thing that struck me about the IA64 is that is closely resembles the design of a register cached stack machine. It isn’t a pure stack machine, but if the register rotation is used correctly, it would be relatively simple to write a good compiler for it.
It’s a major pity that the IA64 is so expensive and seems to have performance problems. Intel simply MUST reduce the price and power consumption just so that the developers can get something happening with it. In the meantime, my money is still with the hammer architecture even though it hasn’t been released yet. I’ll be working hard on our OS to make it 64 bit clean as best as I can and developing two new compilers that will handle both IA64 and the Hammer architectures. I’d like to have a bet both ways, and now that MS has releeased their PE format for the newer archtictures, it is certainly possible for me to build 64 bit versions of Petros sometime soon. All I need is to get my hands on some hardware.
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A CPU should have
1. Low temperature
2. Low cost
3. High speed
It seems the Itanium does not have a good combination of these three.
In particular, too many CPUs run far too hot. Anything that needs a
cooling fan is badly engineered, or at best should be considered
experimental.
“A CPU should have
1. Low temperature
2. Low cost
3. High speed ”
Hey, you just described Mips.
http://www.mips.com/
“Historically, Intel has this remarkable ability to charge a factor of eight for a performance boost of two in microprocessors.”
they are really bad and only after the money. performance of a PII is almost identical to a PIII to a P4. the L1 and L2 cache are all that seems to matter!! let’s not kid ourselves with crappy comparisions and charts!!!