Linked by Thom Holwerda on Thu 18th Aug 2005 16:46 UTC, submitted by Nicholas Blachford
Intel "At next week's Intel developer forum, the firm is due to announce a next generation x86 processor core. The current speculation is this new core is going too be based on one of the existing Pentium M cores. I think it's going to be something completely different."
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Spot on. Rayiner for Inquirer Processor Editor! ;)

The above 4 requirements naturally lead to the following design directions, all of which suggest a design based on the Pentium-M:

1) A short pipeline.

Oh well, at least one thing the Pentium 4 and particularly Prescott with its 31 stages have succeeded in: changing pipeline terminology.

On it debut the Pentium Pro's 12 stage pipeline was considered excessively long when other processor designs had at most eight stages. The PPC604 e.g. had six.

current P4's handle x86-64 code as multiple 16-bit operations

That's almost deliberate obstruction. But surely it does have a 64-bit unit for address arithmetic, doesn't it?

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rayiner Member since:

Ha ha, I think I lied about the 16-bit thing. The P4 had 16-bit "fast" ALUs (it handled a 32-bit operation in two cycles). They ran at 2x the clockspeed, so they were like 2 regular 32-bit ALUs. But I just realized that no 64-bit P4 ever came out. The Prescott (P5?) has 2 32-bit ALUs. They can handle 32-bit operations in 1 clock cycle (but with some limitations that mitigate much of their advantage), but still handle 64-bit ops in multiple clock cycles. The "slow" ALU and the AGUs are all 64-bit.

Intel's basic problem WRT 64-bit support is that they've got the double-speed ALUs. Just getting those ALUs to 32-bits was a pretty trick of engineering. They weren't in a position to just make then 64-bits wide to support x86_64 code.

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