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Mr Braddock wrote:
>it is the internal firmware or logic that kills
>designers or Open Source driver developers.
This shouldn't be a relevant problem.
Internal firmware of Pegasos motherboard is SMART FIRMWARE, a firmware inspired by OPEN FIRMWARE, and it follows same guidelines.
So it there should be no difficulty to port BSD version of Open Firmware to Open Pegasos layout (since the moment it will be completely made open to public).
Think of it as a kernel with device drivers. It provides a simplified view of hardware, so the bootloader/OS doesn't need to know all the specifics. The firmware, however, does. It's not a monolithic silver bullet.
So, has the firmware been released, complete with board-specific routines for CPU/cache/memory/chipset initialization, disk/network/IO drivers, etc?
The only open OF implementation that I know of is the one released by IBM, for their JS20 blades. (64bit unlike the Pegasos; work needed) It needs those board-specifics implemented, AFAIK.
http://www-128.ibm.com/developerworks/power/library/pa-expert5/?ca=...
I'd be surprised if Genesi could open-source Smart Firmware, as it's not their code, AFAIK, but property of CodeGen. They could probably open their Pegasos-specific Forth/C/asm code, for use with the SLOF, but have/will they?




Member since:
2005-07-08
This is only a schematic, as far as I can tell. The real art with modern mobo high-speed design is in the layout. Reference design schematics are very often made available for free from chip producers, since they DO want to encourage you to use their chips. The pinouts on modern digital chips are not really that mystereous; it is the internal firmware or logic that kills designers or Open Source driver developers.
IBM had open-sourced their "Yellow-Knife" PPC motherboard design many years ago, and a few of us in the old OpenPPC project quickly discovered that the schematics are not even one fifth of the battle.
Last year I did a commercial DSP board design, and the FCC certification took a lot longer than the schematic.