Chip firm Intel presented a 65 nanometre dual core multithreaded Xeon with a shared 16MB on die level three cache at the Solid State Conference. The Xeon has 1.328 billion transistors, a 1MB unified L2 cache per core, and has a die size of 435mm2. It delivers 3.4GHz at 1.25 volts and 150 watts TDP, and comes with a 667 and 800MT/s three load front side bus interface. This chip is compatible with existing chipset designs and Intel claims it has the largest cache and device count for an X86 processor.
Intel Shows off Multi-Threaded Xeon Chip
2006-02-07 Intel 6 Comments
Is that debranded hyperthreading? Or are they just repeating ‘dual core’ in different words?