There have been several reports that HP has closed the door on Itanium. Officially, HP will no longer contribute to designs of the CPU and Intel will purchase HP’s development team to end the joint project.
There have been several reports that HP has closed the door on Itanium. Officially, HP will no longer contribute to designs of the CPU and Intel will purchase HP’s development team to end the joint project.
They’ve come to sanity.
I wonder if HP revives the HPPA or Alpha lines, or if they become another boring Intel-only shop.
With everyone going either PowerPC or AMD64 and with HP the only big-name Itainum vendor and with Itanium not being an open ISA to allow dual sourcing of CPUs and with little Itanium-optimized software and with HP still supporting three ISAs and with HP’s brand being diluted by Carly and…
. . .Intel will purchase HP’s development team to end the joint project.
These are people! Surely we have not lapsed into slavery.
I thought in the same line…
HP used to be about innovation. It was always on the leading edge in CPU design. It was a trusted brand name meaning quality. Carly has transformed it into another Dell, just another reseller of chips. Good bye my old friend… I will miss you dearly.
It’s a same to see such a beautiful architecture bungled so completely by over-pricing and poor marketing (I didn’t say ‘not enough’ just ‘poor’). On the other hand maybe I can afford a used Itanium box on ebay now.
What does this EOL sign for the Itanium project mean for openVMS deployment on Itanium (to wich openVMS was ‘recently’ ported)? Is it time to start hoarding alpha machines now or are there other solutions on the way?
If Intel wants to save the Itanium, it better come up with a cheap desktop chip based on the Itanium that still performs significantly better than AMD64 even on non-Itanium optimized code, to spur developers to start writing for the architecture.
If I read the article and understood it correctly, I think HP just got out of CPU design business. It will use Intel (Itanium and Xeon) and AMD CPUs on its server and workstation line, it won’t design CPUs. That I think is a statement that it just was too expensive business, just like most OS vendors don’t have the resources to develop an OS, so we are left with Microsoft (Windows), Sun (Solaris and Linux) and all the previously developing their Unix OSes (Linux)…
Does anyone have any idea of how well or bad Itanium goes (with figures). For example even if SGI is not the biggest company in the world it sells many Altix computers and most of the have many CPUs inside them (even 512 in each box I think)… It is there, it runs Linux and a lot of software written to take advantage of it, but how well does it sell…??
PS. Excuse me for my bad english not native speaker….
Does this mean Intel will now carry on the
IA64 torch alone for another five to ten years or more??
Monkeyboy,
Actually, some posters have gotten ahead of the totallity of the data. I will be posting more later, but the summary is that HP has also announced a US$3B investment in IA-64 servers.
I will likely be posting more later, but the long and short of it is that the re-organization of the development team as Intel instead of a joint HP-Intel project is, on balance, neutral.
There is far more to systems design than purely CPU chip design, and I see HP’s commitment and Intel’s (otherwise, why add the manpower) as positives.
OpenVMS on Integrity works, and I expect release on or about the end of this calendar year, as scheduled (see my recent article on http://www.openvms.org).
– Bob Gezelter, http://www.rlgsc.com
At the same time they just made a $3 Billion commitment:
http://news.com.com/HP+to+make+3+billion+Itanium+commitment/2100-10…
Itanium is an amazing architecture as it is. Just because must people are content with x86 doesn’t make the demand for high end processors any less. “I don’t have Itanium at home -> itanium is not selling” does not prove any point.
so we are left with Microsoft (Windows), Sun (Solaris and Linux) and all the previously developing their Unix OSes (Linux)..
Not to nitpick, but uhh… I think you forgot about a little company there. IBM?
They design CPU’s, OS’s, applications, etc…etc…
Serious question here…
Why does everyone seem to hate the Itanium so much? Having asked that, I understand that it was a poorly marketed product and a black hole of Intel and HP’s R&D budget for the better part of 10 years. I can understand why most businesses have no interest in buying them, but I don’t really understand why everyone seems to HATE the Itanium more than Vlade Divac and France combined.
From a nerd point of view, aren’t the lastest Itanium chips pretty darn fast? Wouldn’t it be cool to have a “big-iron” chip like that somewhere in your house to play with? Can anyone really blame Intel from trying to move away from the x86 architecture and create something better?
I’m no Intel fan at all, but as an owner of some old crappy Sun Ultra workstaions and my new Opteron computer, I do tend to like non-mainstream computers. Hell, UltraSparcs aren’t even fast and a lot of people still like them.
Would any of you really turn down a good deal on an Itanium 2 computer if you found one for sale somewhere dirt cheap?
Don’t bother getting into the nitty-gritty technical details of the chip design or EPIC architecture that everything thinks they know, but no one really understands. I’m just wondering where the hate comes from.
SPARC is pretty big in Japan. There are multiple sparc cpu makers. But I do agree, everything is really going toward PowerPC. IBM has such huge marketing muscle.
Yeap, you are right. I forgot IBM (even if I really shouldn’t since they have this great monster Power5)…
Mistakes hapen. But software wise even IBM doesn’t have the resources to push AIX. and it shows that they would be glad if they didn’t have to (customers investing in the past on AIX hold IBM back).
Anyway, my questions is about how well (or bad) Itanium sells… Does anyone know?
Thanks
I can’t speak for everyone, but I can throw my .02 in.
I don’t hate the Itanium, but look at it from my companies perspective.
(a) We already had our app running on SPARC and POWER (both been 64 bit for along time).
(b) The Itanium had the funny side effect of making 32-bit code run *far* slower than a comparable XEON
(c) Why pay just as much for a Itanium as you could for a genuine SPARC or POWER?
(d) Great, you have a CPU – where is the server thats built around it? Before you point me to HP, please answer (c) above.
So, in the end, the answer is that we didn’t *hate* it, but what did it offer anyone?
AMD had the right idea, offer a modest priced (and modest designed), 64-bit chip. Intel/HP/et al fell victim to over-engineering syndrome IMHO.
http://arstechnica.com/news.ars/post/20041216-4472.html
Well, maybe because it does not have compelling advantages over PPC or SPARC and eats huge amounts of energy…
An Opteron is also much better in price/power/speed.
The French government has ordered a linux-running cluster totalling 4500 dual-core Itaniums (Montecito) to Bull. It should rank #2 on the top500 list at the time it is commissioned (mid 2005) and will be used for numerical simulation of nuclear tests. The first computer to be assigned to that task in France a couple of years ago was a Compaq-designed cluster of AlphaServers, running Tru64.
The Itanium is the epitome of “overengineered”. It’s a mid-’90s take on what the ultimate ISA should be, but unfortunately it’s an ISA so complex that it can’t be implemented in processors or compilers effectively… yet. IA64 may be nice 10 years down after Intel releases several new cores and finally manages a good implementation and compilers can be properly optimized with a good IA64 backend, but for now it’s ISA is simply overkill.
And wasn’t I surprised to discover Itanic was developed right down the road here in Fort Collins… crazy.
Why does everyone seem to hate the Itanium so much?
Aside from xx86 fanboys I don’t think anyone does. I think people hate Intel and HP from patenting anything and everything under the sun relating to ia64 so no one can begin to make compatible chips, and then over pricing the chips. I love the design I hate the companies involved.
Hmm, I’d wonder what happened if someon made a LEON of ia64… probably get sued to no end.
HP is still completely behind Itanium. Besides their recently-announced $3 billion commitment to Itanium over the next 3 years, they’re also the founding sponosr of the Gelato Federation (http://www.gelato.org), a group dedicated to advancing Linux on Itanium.
(b) The Itanium had the funny side effect of making 32-bit code run *far* slower than a comparable XEON
That’s because of eumulation. the Itanium CPU cannot include x86-32 extensions at this time. That’s a HUGE setback for Intel.
Aside from xx86 fanboys I don’t think anyone does.
Uhh, what about the legions of Alpha fans angry that HP is killing off what was formerly the world’s most powerful processor at the hands of what they see as a monumental investment failure that they are standing by because there’s no other way for them to recoup their losses?
Uhh, what about the legions of Alpha fans angry that HP is killing off what was formerly the world’s most powerful processor at the hands of what they see as a monumental investment failure that they are standing by because there’s no other way for them to recoup their losses?
do you really think they hate the processor itself? I mean I can understand hating the companies and begrudging ia64 all that development dough… but actually hating a processor? I mean I assume that when it comes to a processor itself people are more rational and evaluate them on their merits themselves. And when you look the design of the Itanium itself it’s hard not to be impressed.
the $3bn figure is a face-saving gesture intended to make HP look like they’re still serious about Itanic. It’s not actually new money, they’re just re-announcing old money (anyone who follows British politics will be intimately familiar with this trick). See the Reg’s story for details – http://www.theregister.co.uk/2004/12/16/hp_intel_itanic_shift/
On Itanic numbers, they’re pathetic. For the first half of the year, there were a grand total of $606m Itanic sales, worldwide. The total number of *actual systems* shipped is hilarious – in 2Q 2004, precisely 5,665 Itanic boxes were shipped in the entire world, 4,789 of them by HP. Basically the problem Intel has is the Xeon has equal or better price / performance than Itanic but is far less hassle for buyers, suppliers and software writers alike (why rewrite all your software for Itanic when there’s no real benefit to doing so?) Itanic is selling almost entirely in *big* installations at the high-end of the market. It does respectably there (though its market share is single-digit), but the whole point of Itanic was to be The One Enterprise Chip, the CPU that everyone except home users would buy. Intel spent a fantastic amount of money to develop it because of this. If they’d known they were spending a fantastic amount of money to design a niche CPU for big-iron servers, they probably wouldn’t have bothered.
In answer to an earlier post, no. They will not be an intel only shop. They are about to put out a few servers that have AMD64 chips in them
I also wonder why people don’t like the Itanium and bash it so. I think maybe there always needs to be something for pundits to be critical of no matter what the things true nature.
As an assembly langauge programmer who has shipped highly successful products that were 100% hand written in assembly language, the EPIC processor design is a dream from an assembly language programmers point of view. Don’t let anyone tell you otherwise! Tons of wide registers, cool instruction level parrallelism, awesome predicate registers for reducing branch prediction delays, etc… It’s simply awesome! Yes, I’d not want to write too much assembly language code by hand for any modern processor, that’s what compilers are for, but the optimization opportunities presented by EPIC are, well, epic. (Groan, sorry about that). As is the potential for cool hand written assembly language stuff, wow, it’s simply impressive.
What I can’t figure out is why Intel can’t get their marketing strategies straightened out. I’ve written about it at 64bits.net; see “The Beauty of Itanium and The Attraction of the AMD64 Beast” in the item “The End of Itanium”.
http://www.64bit.net
I’d love to work on a funded Itanium based project. Got one? Call me!
woops, that’s 64bitS.net not [i]64bit.net[i].
What I can’t figure out is why Intel can’t get their marketing strategies straightened out. I’ve written about it at 64bits.net; see “The Beauty of Itanium and The Attraction of the AMD64 Beast” in the item “The End of Itanium”.
http://www.64bits.net
“As an assembly langauge programmer who has shipped highly successful products that were 100% hand written in assembly language, ”
…as a compiler writer I must tell you have no idea what a pain in the a** EPIC is to optimize. I have never ever heard anyone who has worked with EPIC directly say any good thing about writing assembly for it. So if indeed you have actually developed and shipped a product for IA64 written by hand I must congratulate you.
…since I also do architecture research for my job as a Ph.D. student, EPIC is such a nightmare that Intel is still unable to provide an Out of Order implementation of the architecture.
It’s a same to see such a beautiful architecture bungled so completely by over-pricing and poor marketing…
I don’t know, I always thought of Itanium as being ridiculously overpriced and unbearably slow. I think “beautiful” would be the last adjective to pop to mind in connection with the Itanium chip.
do you really think they hate the processor itself? I mean I can understand hating the companies and begrudging ia64 all that development dough… but actually hating a processor? I mean I assume that when it comes to a processor itself people are more rational and evaluate them on their merits themselves. And when you look the design of the Itanium itself it’s hard not to be impressed.
It’s an overdesigned ISA too complicated to be properly optimized for, designed around mid-90’s concepts about the future of processor design which has since proven unfeasible.
There is nothing to hate about the itanium, as a number cruncher it was more or less at the top of the list until IBM came out with power. As a super computer componant it is very good, as a general server it is pretty bad partly because it costs so much.
I worked for DEC when they developed and produced the first alpha ( 1984 – 1986 ) and they spent huge amounts of money on it as it was the replacement for VAX. When it arrived marketing could only think in terms of VAX killer. DEC lost money, compaq took them over, HP took them over and are about to murder what is still a fantastic architecture.
Hate the itanium, no it’s a good chip in its own right and given the correct circumstances it flies along.
Hate HP, best not to go there
“I worked for DEC when they developed and produced the first alpha ( 1984 – 1986 )”
Really? Then you were way ahead the rest of your company then, given that the alpha was produced in the early 90s…
I never said that I’d written much or any Itanium assembly code. Unfortunatley I’ve not been able to use an Itanium, but I have studied the instruction set extensively and find it facinating. I look forward to the highly unlikely event of Intel getting their marketing strategies corrected so that I can get a chance to use the Itanium. In the meantime we are stuck with traditional architectures such as AMD-64 and Power.
By the way, don’t get me wrong, I’m excited about replacing all my boxes with the next generation 64 bit computers. Which will likely be AMD-64 cpus due to Intel’s lack of a mass market Itanium strategy. It’s just that from a design point of view the better CPU designs just keep failing to capture the market lead. Intel’s 386 crushed the MC68040. Pentium crushed the Alpha. AMD-64 is crushing the Itanium. Sigh… time to give up and simply study the worst designed chips.
YOU might not like to write compilers for the EPIC architecture. Yes, it’s quite different from what most compiler writers are used to, but it’s designed with optimizations in mind. Time to learn some new optimization techniques, like the ones the Itanium designers had in mind? Maybe some of those techniques will also work on traditional architectures such as Pentium and Power?
What’s so difficult about compiling to use the EPIC predicate registers? They are an obvious and easy optimization to compile for that reduces the likelyhood of branch mispredictions.
It amazes me. Intel actually listened to all the complaining that people did about the Intel 486/Pentium architecture and designed a CPU that corrected those defects. A CPU to address the shortage of registers, the horrible FPU design , etc… of the 386/486/Pentium line. The Itanium CPU provides so much more than others and people still attack it. Yeesh. Chip designers can’t get no respect.
What really is so hard about writing compilers for the Itanium? Why is it ugly?
It’s all a matter of taste but I prefer very much RISC ISA such as Alpha or Power ISA than IA-64’s VLIW ISA.
[ I find very funny that you say we’re stuck with Power architecture. ]
IMHO Intel made a mistake when it used a VLIW architecture, they provide good FP performance but they suck at integer calculations..
The earlier posting in response to Peter’s posting about Itanium deserves a response.
Just to get the issues straight, my background includes: 25+ years of writing assembler on a wide range of platforms, from microcontrollers to supercomputers; familiarity with EPIC and VLIW architectures from the time of the 1980’s, and time spent on compiler code generation and optimization. While I didn’t finish my Ph.D. (perhaps some day), I do have all of the points beyond my Masters (of course in Computer Science).
Yes, writing hand-written code for an EPIC or VLIW architecture is challenging, but a bit of a pain. I have analyzed object codes on VLIW machines, and while it is certainly different than a classic CISC or RISC von Neumann machine, it is quite feasible, but tedious.
The comment “… Intel is not able to manage an Out of Order implementation” is a red herring. EPIC is not about the call stack changes, nor is it about the predicate registers, although those certainly are large positives. EPIC is what its name states, Explicit Parallel Instruction Computing”. An Out of Order implementation is not intended by the architecture. One of the most complex parts of the classic CISC and RISC designs is the code reordering operations which are done completely “behind the back” of the compiler. The logic involved in such wizardy accounts for a large chunk of high performance RISC chips. Making the parallelism explicit, and letting compilers optimize their object code unambiguously is the goal of EPIC.
Multithreading in a single CPU, by contrast, is feasible and in the works.
I am mostly out of time this morning, so I will have to signoff at this point.
– Bob Gezelter, http://www.rlgsc.com
Itanium complexity may be compared with DSPs which cannot unleash all their power without hand coding the signal processing algorithms.
Itanium design is based on the assumption that some complexity can be transferred from hardware to the compiler. Explicitly Parallel Instructions as about transferring a part of the superscalar instruction dispatch to the compiler.
Itanium compiler problems is also RISC vs CISC in another way. A simple instruction set permits a great deal of hardware tuning with different generations of CPUs ( the naive x86 instruction set has proven to allow huge hardware scalabilty ). Today’s CPU ISA are an abstraction of the real way the processor works : For example, the fact that a processor may have any number of integer unit is hidden to the software, which allows the same binary code to benefit from all the resources of the CPU whereas in a DSP style design, there is no place to enhance the CPU while keeping the same software, the same compilers, … ( SPARCs even allows some kind of ajustable register number )
I think that in the future, CPUs will become more and more like virtual machines. The way they are programmed will be much different from the way they actually work ( with rename registers, instructions reordering, superscalar architecture, hyperthreading, … ). Intel has bet on the opposite. The next step is about multi-core CPUs which is another way of scaling a CPU without changing the [multithread-aware-]software.
( It is no excuse from the fact that x86 ISA is a real mess and I would have preferred to see it die. )
> The next step is about multi-core CPUs which is another way of scaling a CPU without changing the [multithread-aware-] software.
Uh? You can’t say ‘without changing software’ and saying ‘multithread-aware’ in the same sentence: most software are not multithread-aware, so to make them perform well on multi-core CPU, you have to modify the software!
I find also very funny that you define x86 as simple, usually it is considered as CISC, you know..
Programmers, just a bunch of meat hanging on the rack to these companies.
As many have mentioned, EPIC is mainly about making all Out-Of-Order (OOO) execution explicit. This saves lots of on-chip resources and should make a chip smaller, if anything (compared to a RISC chip with the same execution units inside).
So, while the Itanic is a huge chip, because tuned for super-high-speed, it is a nice idea (just like the Transmeta CPUs).
To the compiler people: if even something like a CPU frontend (say on the P4 or PPC970) can take “normal” code and create an OOO-schedule of that code for the internal execution units, and all that (1) in real time and (2) in a simple hardware implementation that doesn’t allow for huge algorithms, then any compiler should be able to schedule its code nicely for EPIC.
The biggest mistake Intel+HP made after coming up with a beautiful design was bloating the chip with (!!!) a hardware implementation of the whole x86 instruction set and letting this influence the design. OF COURSE a hardware emulation of x86 on EPIC was much slower than a tuned x86 chip, and who would have bought an (expensive!) Itanic in the first place TO RUN LEGACY CODE on it, instead of recompiling it with a new compiler?? While some x86 compatibility makes sense for Intel, why the hell didn’t they put the emulation where it belongs, by implementing a nice software JIT layer?? Sun managed to do just that for the whole JVM on Itanic.
Just my 5c
As promised, a review of the facts, not the FUD, about the last few days HP-Intel announcements regarding Itanium can be found at: http://www.openvms.org/stories.php?story=04/12/17/1677470
– Bob Gezelter, http://www.rlgsc.com
renoX wrote: “It’s all a matter of taste but I prefer very much RISC ISA such as Alpha or Power ISA than IA-64’s VLIW ISA.”
renoX, if it’s all a matter of taste (which I don’t fully agree with) then I very much prefer EPIC over RISC and RISC over CISC with CISC being better than nothing.
Unfortunately our tastes have nothing to do with the success of a processor in the marketplace. We are stuck with the fine AMD-64 extensions of Pentium, a vast improvement on the IA-32 Pentium, no doubt, but we could have had so much more… it could have been EPIC…
“[ I find very funny that you say we’re stuck with Power architecture. ]”
PA-Risc, Power/PowerPC, Sparc, Alpha, Motorola MC68040, MIPS, and ARM are all awesome processors. It’s just that the EPIC is a newer gerneration beyond RISC. I like progress. I like registers, predicate registers, instruction level parallelism, control over instruction bundles, etc… and did I mention that I like registers, registers, registers. Regardless of register renaming as a compiler technique, to an assembly language programmer an abundance of registers opens new horizons.
With 128 integer registers, 128 floating point registers and 64 predicate registers at your disposal the EPIC architecture enables algorithms in three dimensional graphics and audio applications to go wild and get fast! In effect the Itanium almost becomes a variant of a Field Programmable Gate Array (FPGA) processor, since it has multiple instructions that can be executed at once (currently 6 instructions per cycle but that could be extended to 128+). But it has an advantage over FPGA processors in that it’s easier to program since it’s still pretty much a processor that we are familar with.
I like some of the Field Programmable Gate Array (FPGA) and “cell” processors that are coming. Can you imagine Input-Output (IO) Processors that ran completely through FPGA? Kinda like DMA on super steriods. Some of the 3d graphics processors are getting these capabilies. Simply awesome.
Projecting forward: if Intel takes the Itanium design to it’s ultimate implementation each chip could have 128-256+ processing units on board and execute 128-256+ insturctions at the same time. Obviously most software doesn’t have that much instruction level parallelism so such a chip would also need to have multiple cores that share their processing units. An 8 core Itanium chip might have 16 processing units per core for 128 processing units to be shared amoungst all the cores.
(For a discussion of Itanium 2’s “Execution Resources” See page 22 of http://www.dig64.org/More_on_DIG64/Itanium2_white_paper_public.pdf ).
“IMHO Intel made a mistake when it used a VLIW architecture, they provide good FP performance but they suck at integer calculations..
As we have seen Intel has had a lot of problems getting the Itanium into production with speeds that are acceptable, yet alone breathtaking. Give them time to get itanium’s performance right (assuming they don’t abandon the Itanium) and you might be pleasently suprised.
Some will say that because Intel is taking time to get it right is a reason that RISC is better, because it’s easier to produce RISC chips, but the Pentium has shown awesome growth potential over it’s life span, which I think demonstrates that CISC and RISC are both viable designs. It demonstrates that you can take a simple or a complex approach and achieve results. Wolfram has shown this in “A New Kind of Science” ( http://WolframScience.com ).
I wonder if it’s taking Intel so long to get it right because Itanium is a new instruction set design? One that’s sufficiently different that the chip design patterns from Pentium don’t apply and that new chip design patterns needed (and maybe still need) to be developed. The Pentium design at 4ghz is quite different from the i386! Maybe the Itanium is simply hovering around it’s parallel of the i386 implemetation? Maybe when Itanium gets to it’s parallel of the Pentium in performance it will really sing.
Unfortunatly the market isn’t likely to give them too many more chances with AMD-64 rapidly capturing vast marketshare. It also simply could be that IA32 is unstopable for compatibilty reasons. Maybe no one, not even Intel, can overcome the success of the IA32 design! And that’s the beauty of AMD’s marketing strategy! At least AMD-64 is an improvement over IA-32, and that’s processor progress that I can live with, even as I dream for more!
Anonymous (IP: —.cruzio.com) wrote: “…as a compiler writer I must tell you have no idea what a pain in the a** EPIC is to optimize.”
Rather than telling me what I know or don’t know how about telling us: specifically why is EPIC a pain to optimize for? Please give detailed examples.
>It’s just that the EPIC is a newer gerneration beyond RISC
Beyond RISC? OK, it came later but this doesn’t mean it is superior. VLIW were tried EPIC before and failed.
The reason? Too much complexity pushed on the compilers which were unable to compensate the lack of ‘out of order execution’ that RISC&CISC have now (the high performance one).
>did I mention that I like registers, registers, registers.
Registers don’t come for free: the higher number of register available, the slower the access time to the register set is, also the higher number of register used, the slower a context switch is.
Like cache, increasing the number of register gives a reduced improvement: going from 8(6) to 16 as from x86 to x86-64 is a big improvement, 16 to 32 (RISC) may help too in code with lots of computation, 32 to 128 ?
I’m not sure that this will help except in Fortran programs..
> As we have seen Intel has had a lot of problems getting the Itanium into production with speeds that are acceptable,
I’d bet that this because their ISA is so complex that they had such hard time to implement it, no wonder people don’t like the ISA: if it’s too complex to be implemented with a reasonable cost by one of the biggest CPU makers, maybe there is a problem?
>Give them time to get itanium’s performance right
That’s funny, I hear the same thing from itanium’s bakers (which are less numerous each day) since a long time!
“ >Give them time to get itanium’s performance right
That’s funny, I hear the same thing from itanium’s bakers (which are less numerous each day) since a long time!
Moore’s law and a lot of work by people at Intel made the i386 into something special, the current generation Pentium/Xenon. Heck even the AMD-64 is decended from the lowly i386 processor. So it’s not “funny” to hear this sort of comment, it naturally reflects the stages of design over multiple generations of implementations. Given the resources and (assuming the) commitment Intel will keep working their Itanium design and implementations. It’s only had two generations so far, how many has the Pentium had? How many have other chips had?
“Registers don’t come for free”
Yes, registers don’t come for free, but they sure can make a difference. The Itanium design has features to reduce these costs.
“Most procedure calls only require a few new registers to be allocated, so many calls can be made before exceeding the physical limits of the register file. If the program returns without exceeding the physical register stack size, then no
memory references are required to save and restore register contents. This is an effective method to reduce memory traffic and speed up procedure calls and returns.”
– Page 8 of http://www.dig64.org/More_on_DIG64/Itanium2_white_paper_public.pdf
I am not a backer of the Itanium in the sense that I don’t have any financial stake in it at this time. I don’t own one. I don’t even own Intel stock. I’m simply someone who would like to see the Itanium succeed for Intel (and hopefully other sources such as AMD) and have it replace the Pentium as the major market leader. As I’ve said before this doesn’t look likely at this point in time due to the emergence of the AMD-64 (which is at least better than the IA-32).
“It’s only had two generations so far, how many has the Pentium had? How many have other chips had?”
Well…
8086 -> 80186 -> 80286 -> 80386 -> 80486 -> Pentium -> Pentium II -> Pentium III -> Pentium IV = 9. But the difference is *every single one of those* was a profit-making success (well, um, I can’t vouch for the 186, but apparently it was used in printers or something). Obviously the more recent ones are better than the earlier ones (duh). But none of the previous ones tanked, unlike Itanium.
8086 -> 80186 -> 80286 -> 80386 -> 80486 -> Pentium -> Pentium II -> Pentium III -> Pentium IV = 9
Yes, that’s success, and success that even Intel is having trouble beating.
The market was much different when the early generations of Pentium line came into existance. It was easier to succeed with less competition. The market now is vicious with multiple competitors with excellent chip products that work and work very well thank you. It’s not a suprise that the Itanium has failed so far – EVERY OTHER 64 bit chip has!!! Alpha, PA-RISC, SPARC, MIPS, Power. You name it, none of these awesome chips have touched the Pentium mass market. It takes a continuation of IA32 in the form of the 64 Instruction Set Extensions glued on by AMD to be the first crack into 64 bit computing on the mass scale. So much for pureity of a design trumping marketing success. Sure the AMD-64 extensions have a beautiy of their own, but they aren’t a pure 64 bit processor designed from the gound up. All of those have failed to capture the mass market. So if you blast at Itanium for it’s failure in this regard you must, to be accurate, to reveal your unbiased vantage point of the industry, you are compelled – based on the facts – to blast these other processors for the same failings. Except of course the quasimoto that the AMD-64 represents as it looks like a resounding success. Even Intel had to admit it and change course.
It doesn’t help that Intel has mucked up no the execution by sticking to the high end market. The lack of a Itanium-Pentium fusion that works has stifled Itanium, but that doesn’t relfect on the Instruction Set Design. You are confusing market success with design qualities. As anyone who takes marketing 101 knows the best mouse trap isn’t necessarily the one that top market share; usually it’s the clunky mouse trap that works ok that succeeds most.
The beauty of Itanium isn’t marred by it’s marketing penetration as these are orthogonal dimensions.
The point is that the Itanium is in it’s infancy and IF Intel keeps its efforts up with it it could be a force to be reconned with. This is especially the case if Intel releases a version with a potent IA32-AMD-64 capability and performance that matches. As long as the price is right mass numbers of people then have a realistic choice: Itanium-IA32+AMD64 in a single package for just about the same price as a standalone IA32-AMD64 from Intel or AMD. Now we’d be talking. I’d take the Intel chip under these conditions.
A high performance fusion with Pention at a market price that competes with AMD will save Itanium Intel. Are you listening? Otherwise forget it. Now where is that cute quasimoto of an AMD-64 that I play with? Get down from the bell tower and into the marketplace courtyard… ah there you are… now what OS to run on it? Linux, FreeBSD, Zoku?
Development takes time to get right, yes but in the meantime IBM is still producing its POWER CPU which are more or less equivalent on performance than an Itanium2.
So, 1) Intel has already had lots of time to develop their Itanium
2) it has produced nothing superior to existing RISC competitors while spending *a lot* of money.
It would be very interesting to compare the amount of money spend by Intel (and HP) on their Itanium, Itanium2 and what IBM spent on developing their Power CPU.
Also about the register thing: I said ‘context switch’ such as when you change the running process, your answer belongs to function calls.
Register window is a nice feature (started on RISC SPARC if memory serves),but it also slows down register access because essentialy it adds one level of indirection.
I’m no expert, but it seems like recent CPU trends may make explicit parallelism less relevant. Most companies seem to be moving towards emphasizing multithreaded performance (hyperthreading, Niagara, multi-core, etc.) over single threaded performance. EPIC (in my simplistic view) seems to be all about moving scheduling decisions out of the hardware and into the compiler. Hyperthreading (and other simultaneous multithreading schemes) are all about dynamically managing chip resources on the CPU.
My question is whether explicit parallism and simultaneous multithreading are inherently incompatible. One you’ve got a mix of threads running on a single CPU, are the “explicitly parallel” decisions made by an EPIC compiler useful. It would seem to limit the flexibility of the on-CPU scheduler. In other terms, EPIC seems to benefit from having the compiler know about the details of the execution system while SMT seems to make the execution system dynamic (i.e. the resources available to any thread vary based on other threads running on that CPU).
I’m not saying EPIC is bad. It seems very well suited to a heavily multicore / simple-core system (like Niagara). Maybe I’m just babbling at this point…
“EPIC seems to benefit from having the compiler know about the details of the execution system while SMT seems to make the execution system dynamic ”
I don’t see how that’s the case.
It seems to me that the Instruction Level Parallelism and simultaneous multi-threading /hyper-threading are orthogonal, especially since the Itanium2 chip has two cores with six instruction units each.
Why do you think that it’s a problem? Why would you compile programs any differently under single thread load or multi-thread loads?
Obviously the vast majority of processors today are running with multiple threads. Any chip designers that didn’t take that into account… well…
What do people’s experience with Itanium2 have to say? What do the benchmarks have to say?
IBM is still producing its POWER CPU which are more or less equivalent on performance than an Itanium2.
So what?
As I said the Power/PowerPC lines of CPUs are excellent chips designs. The RISC chip to market story is an old one, and a good one. I’m all for simple designs, as you can read at http://www.Smalltalk.org.
At the present time IBM hasn’t managed to outseat the Pentium in it’s dominant pc market position so from that perspective it’s failed just like Alpha, MC68040, MIPS, Sparc, PA-RISC, etc… While IBM has failed there it’s had successes elsewhere which is awesome for IBM and it’s customers. I’d love to see an eight core Power chip in the Apple (G8?). It’s coming, but when Apple?
It’s clear that EPIC isn’t a RISC design, however much influence RISC had on the design of EPIC (from what I understand EPIC has some elements of RISC thus it’s a next generation). From everything that I’ve read EPIC has been a much larger undertaking for Intel and HP than they thought at first. Yes, EPIC is more complex than a simple RISC design. Yes, Intel and HP have seemingly – from the limited information and points of view that we have from press reports – had difficulties developing it. I think that any new technology, especially one as different as EPIC, simply takes time to get right. It’s a new unfamilar chip architecture, so the old chip implementation design rules likly don’t work. They have to invent how to implement it in a performant way. It took time for DEC to get Alpha right, it took time for Motorola to get the MC68040 right. Intel has two working Itanium chip generations produced with more on the way. While they seem to have bitten off more than they can chew, they seem to be producing results.
You might be critical but they are the ones working at improving the design implementations. It’s easy to be critical, that doesn’t take any work. What’s hard is to create and to create in a highly competitive environment with highly successful competitors.
“the higher number of register used, the slower a context switch is”
Yes, this is a concern that I’ve had for a while and don’t actually know the answer to. So, let’s find out.
Does anyone who has worked with or studied the Itanium in depth know about this? Please provided detailed examples.
From the net:
“It all depends on how much state you save/restore. If all the fp registers get saved/restored, that will be slower but many apps only use integer registers (and perhaps f2-f31), so they’ll never need to save/restore f32-f127 etc.”
http://www.gelato.org/community/view_linear.php?id=10_90&from=autho…
The same applies to the main Integer Registers, most applications likely will just use the first 31 (r1 – r31).
They go on to say:
“f32-f127 can be lazily saved/restored”
This is a common thing to do on current processors like the Pentium. See http://www.netbsd.org/Documentation/kernel/lazyfpu.html
“The Itanium processor has 128 integer registers, of which the top 96 are part of a rotating register stack. The OS is required to “spill” the registers out to memory when needed when the register stack overflows in deep call stacks. … As eluded above, the register environment for the architecture is more robust than x86 based systems. The OS is required to save and restore a different, larger set of registers during thread context switches. In database environments, however, context switches are driven by IO processing. The Itanium architecture reduces IO requirements, and therefore context switches, through large memory configurations.”
http://msdn.microsoft.com/library/default.asp?url=/library/en-us/dn…
Some of the nitty gritty details are here:
http://h21007.www2.hp.com/dspp/files/unprotected/threads/Itaniumthr…
Pages 15 and 16 describe how Linux for the Itanium handles the large register set. Here is what HP has to say: “manage state efficiently by taking advantage of software and hardware conventions: Don’t save/restore registers needlessly. Don’t save state that can be reconstructed. Manage state lazily where reasonable.”
http://www.kernel.org/pub/linux/kernel/people/helgaas/tokyo.pdf
On the register issue it seems that there are solutions to reduce the costs, but above all don’t save/restore state needlessly. It’s a cost benefit tradeoff and as such each application needs to make it’s choices. There could be a large benefit to using all the regsiters and the Context Switch overhead may be small in comparison.
ps. Tuomo Kortesmaa implemented an OS Nano Kernel for the IA-64 in a rapid amount of time. Awesome!
http://users.evtek.fi/~tk/
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8086 -> 80186 -> 80286 -> 80386 -> 80486 -> Pentium -> Pentium II -> Pentium III -> Pentium IV = 9
Yes, that’s success, and success that even Intel is having trouble beating.
The market was much different when the early generations of Pentium line came into existance. It was easier to succeed with less competition. The market now is vicious with multiple competitors with excellent chip products that work and work very well thank you.
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Yet Intel seems to have done a fine job of eliminating much of the competition. Even AMD itself was on the edge of failure more than once, just managed to survive. In fact, even today there are no companies in the work capable of matching Intel’s manufacturing capacity. I agree that, “The market now is vicious …” because Intel is ruthless and kills all competition it can. If anything the market has been in Intel dominated and controlled (see Dell).
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It’s not a suprise that the Itanium has failed so far – EVERY OTHER 64 bit chip has!!! Alpha, PA-RISC, SPARC, MIPS, Power. You name it, none of these awesome chips have touched the Pentium mass market.
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Of course not. Who designed and built Alpha for example? Did DEC sell PCs? Did they design Alpah for the mass market? Is Ferrari a failure because it sells so few cars in America compared to Honda and Toyota? You are mixing things. Most of the listed processors were never designed for mass market, including Itanium. Itanium has not failed in the mass market because it has never been sold in the mass market. This comparison makes no sense at all.
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It takes a continuation of IA32 in the form of the 64 Instruction Set Extensions glued on by AMD to be the first crack into 64 bit computing on the mass scale. So much for pureity of a design trumping marketing success. Sure the AMD-64 extensions have a beautiy of their own, but they aren’t a pure 64 bit processor designed from the gound up.
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The real and principal reason why no 64 bit processors entered the mass scale yet is simply that there was no need for it until now. Intel itself has said as much and for the most part they are correct. All of the multimedia efforts at Intel were the result of their need to push the processing requiremens in PCs to create the need for 64 bits. 64 bits were simply not needed in the past, so no company has even bothered to try before. It has nothing to do with the sucess of instruction sets, but everything to do with the old instruction set and processor implementations satisfying all desktop PC processing needs and the some.
The new developments pushing the need for 64 bits are:
1) new games keep pushing the envelope, need more processing, memory, etc. The game industyr has grown so much that it has become difficult to ignore
2) Windows server has matured to the point that it is being taken seriosly and is starting to spread, again new growing market
These 2 combined are the sufficient size market to warrant attempting to create a 64 bit solution for mass market. Nevertheless, still today most office apps ad home apps are just fine on 32 bits.
So instructions sets have little to do why there haven’t been many 64 bit solutions for mass market.
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It doesn’t help that Intel has mucked up no the execution by sticking to the high end market. The lack of a Itanium-Pentium fusion that works has stifled Itanium, but that doesn’t relfect on the Instruction Set Design. You are confusing market success with design qualities. As anyone who takes marketing 101 knows the best mouse trap isn’t necessarily the one that top market share; usually it’s the clunky mouse trap that works ok that succeeds most.
The beauty of Itanium isn’t marred by it’s marketing penetration as these are orthogonal dimensions.
The point is that the Itanium is in it’s infancy and IF Intel keeps its efforts up with it it could be a force to be reconned with. This is especially the case if Intel releases a version with a potent IA32-AMD-64 capability and performance that matches. As long as the price is right mass numbers of people then have a realistic choice: Itanium-IA32+AMD64 in a single package for just about the same price as a standalone IA32-AMD64 from Intel or AMD. Now we’d be talking. I’d take the Intel chip under these conditions.
A high performance fusion with Pention at a market price that competes with AMD will save Itanium Intel. Are you listening? Otherwise forget it. Now where is that cute quasimoto of an AMD-64 that I play with? Get down from the bell tower and into the marketplace courtyard… ah there you are… now what OS to run on it? Linux, FreeBSD, Zoku?
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Sure high price is an issues, but not an insurmountable obstacle. Many other RISC chips are still expensive, yet still have a significant following. Linux, Web and other new exciting technologies didn’t need marketing money, promotion, etc. If it really is a good technology then develpoers embrace of their own free will. On the other hand if it is difficult to handle and not worth the hassle it will be avoided. There is only so much Intel can do.
It is great that Intel attempted to make a break and start with a clean slate. However, in the end developers will decide if the new instruction set is good or not. The fact that so much time has passed and there are still few developers eager to make use if it speaks a lot for (against) it.
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As I said the Power/PowerPC lines of CPUs are excellent chips designs. The RISC chip to market story is an old one, and a good one. I’m all for simple designs, as you can read at http://www.Smalltalk.org.
At the present time IBM hasn’t managed to outseat the Pentium in it’s dominant pc market position so from that perspective it’s failed just like Alpha, MC68040, MIPS, Sparc, PA-RISC, etc… While IBM has failed there it’s had successes elsewhere which is awesome for IBM and it’s customers. I’d love to see an eight core Power chip in the Apple (G8?). It’s coming, but when Apple?
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Of course IBM did not outseat Pentium line because it never tried!!!! This is silly beyond belief. Which store did you find IBM branded PC based on a Power chip for sale????? On the contrary, Power has proven to be fantastic success for IBM in the server space. On the other hand Power for Apple has been a failure to some extent. Apple machines are competing against PCs, that is a fair comparison. You can compare Apple/Power to Pentium market share and claim that Power is a failure, fine. But IBM’s Power is a completely different.
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It’s clear that EPIC isn’t a RISC design, however much influence RISC had on the design of EPIC (from what I understand EPIC has some elements of RISC thus it’s a next generation). From everything that I’ve read EPIC has been a much larger undertaking for Intel and HP than they thought at first. Yes, EPIC is more complex than a simple RISC design. Yes, Intel and HP have seemingly – from the limited information and points of view that we have from press reports – had difficulties developing it. I think that any new technology, especially one as different as EPIC, simply takes time to get right. It’s a new unfamilar chip architecture, so the old chip implementation design rules likly don’t work. They have to invent how to implement it in a performant way. It took time for DEC to get Alpha right, it took time for Motorola to get the MC68040 right. Intel has two working Itanium chip generations produced with more on the way. While they seem to have bitten off more than they can chew, they seem to be producing results.
You might be critical but they are the ones working at improving the design implementations. It’s easy to be critical, that doesn’t take any work. What’s hard is to create and to create in a highly competitive environment with highly successful competitors.
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Fair enough. There are a lot of unknowns, probably lot of challenges. More time, sure. If they are really convinces that the design works then by all means, they should ignore the critics.
The primary criticism is that they have been working on it for a long time, spent a lot of money, and yet still seem to be bogged down in delays and unable to reach the promised performance that is supposed to be significantly over the current offerings. The point is that the current designs, both IA32 and RISC have basically squeezed out as much parallelism as possible from a single core and it is going to be much easier/cheaper to build multiple cores then keep pushing single core parallelism and frequency. So far it has been the case as even Intel is dropping out of the frequency race. So the onus is on Intel to prove that it is right. Hasn’t done it yet and we won’t wait for ever.