Guest post by GlobalFoundries, the former manufacturing arm of AMD, has announced they will have a 28-nanometer high-k metal gate process available in the second half of 2010. GlobalFoundries developed the 28nm process in conjunction with IBM, Chartered Semiconductors, Infineon Technologies, Samsung Electronics, and STMicroelectronics as part of the IBM Technology Alliance. According to The Tech Report, the new process will reportedly enable “40% better performance, over 20% lower power consumption, and 50% smaller die areas” versus the current 45nm process, but it was not mentioned what kind of performance numbers the 28nm process will have compared to the upcoming 32nm process.
Speaking of the 32nm process, GlobalFoundries is set to kick off production of 32nm chips in the first half of 2010. Producing 32nm chips 6 months after Intel, rather then the 12-14 month lag time under AMD, would be a big success for the new company. Intel’s manufacturing capabilities have been one of it’s strongest assets in it’s battle with AMD and the rest of the semiconductor industry at large. IBM has been very bullish on the 32nm node for quite sometime, even calling the 45nm process a “weak node”, so the clipping of at least 6 months is probably to be expected.
Scott Fulton at Betanews has some interesting commentary on the subject, except he misses the part about the 28nm node being targeted at GPUs and chipsets rather then CPUs.
GlobalFoundries, not GlobalFoundAries (extra A, used everywhere).
You’re right, fixed it. Thanks!
Thanks! Can you delete this thread then? It’s become irrelevant and could confuse people unnecessarily
How did GlobalFoundries manage to do this so soon after being established? They’re still ordering T-shirts and moving plastic potplants into the office! Well, not quite, but it’s quite a big thing to accomplish in such a short period of time… reckon it was really all those other players who did it?
It seems like there is a consolidation of fabs they already own to make this happen. I would surely like to see them cook Intel’s goose and make AMD competitive again.
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As someone who used to work in the semiconductor industry, you’d be surprised what’s in the R&D arsenal at chip fabs. Not to mention startups usually comprise themselves of engineering academia garnered from the competition.
Fab processes don’t happen overnight, AMD was already working on 22nm before the split, and their partnership with IBM had been going on for a while. They most definitively did not start from scratch after the spin off.
You realize of course that when you spin off an existing business they don’t start from scratch.
What I want to know is if they’ve done anything clever about subthreshold leakage current. Basically, when a transistor is “off”, it still conducts. At 180nm, the ratio between “on” (dynamic) current and “off” (static) current was about 1000. At 32nm, they’re about equal, meaning that a transistor conducts only about twice as much when on as when it’s off. Among other things (like process variation that makes transistor switching characteristics increasingly unpredictable), this is responsible for a slow-down in expected performance and power improvements from smaller geometries.
Interesting post. Learned something new about the transistors thanks!
I admit to knowing very little about how transistors work, but I think http://en.wikipedia.org/wiki/High-k_dielectric covers at least one way processor manufacturers are reducing leakage current.
I’m still waiting for photon switches. Anyone has an idea of current development in that area?
Actually, no. High-k dielectrics reduce quantum tunneling through the gate insulator. The problem I’m talking about is conduction through the channel (where it would normally conduct, but it shouldn’t because the transistor is “off”).
In some instances they will need more aggressive clock gating approaches, where they can isolate parts of the circuit and shut them off completely (although there is a penalty for re-starting that section of the circuit).
A lot of the research seems to be directed into reducing operational temperature, as temperature seems to be one of the principal components of leakage. I.e. cooler circuits = lower leakage.
Although the switching characteristics are not so “random” but there is a clear penalty for “wasted” power due to leakage.