Linked by Thom Holwerda on Thu 16th Nov 2017 21:56 UTC
Linux

The RISC-V port was just merged to Linux a few minutes ago. This means we will be in the 4.15 release, which should be out about 10 weeks from last Sunday. As soon as the tarballs are created, the RISC-V Linux ABI will be stable, and since we'll ideally be in a glibc release that comes out soon after that we'll be fully ABI stable by early in February.

RISC-V is a completely free and open ISA that hasn't seen much adoption just yet.

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Lennie
Member since:
2007-09-22

It still needs (virtual) hardware specific support to actually run on anything if I'm not mistaken.

Out of tree driver do exist, again if memory serves me right.

See here for the source code:

https://github.com/riscv

Some of the reasons why we need something like RISC-V:

https://www.youtube.com/watch?v=zXwy65d_tu8

Edited 2017-11-16 22:19 UTC

Reply Score: 4

Comment by judgen
by judgen on Thu 16th Nov 2017 22:19 UTC
judgen
Member since:
2006-07-12

Is RISC V used in the Talos workstations?

Reply Score: 1

RE: Comment by judgen
by zizban on Thu 16th Nov 2017 23:29 UTC in reply to "Comment by judgen"
zizban Member since:
2005-07-06

No, POWER9 chips.

Reply Score: 3

Adoption
by JLF65 on Fri 17th Nov 2017 18:06 UTC
JLF65
Member since:
2005-07-06

Adopting new hardware depends on there being a useful OS for the hardware. Making linux for RISC-V means now there's actually something to run on RISC-V hardware, so adoption should rise dramatically. Getting a repository for recompiled packages would also help increase adoption. When a RISC-V version of Ubuntu with all the associated packages is available, you'll see RISC-V computers in the market.

Reply Score: 1

RE: Adoption
by tylerdurden on Fri 17th Nov 2017 21:25 UTC in reply to "Adoption"
tylerdurden Member since:
2009-03-17

ubuntu is not such a force on the desktop as to drive the adoption of a specific architecture.

RISC-V is going to be mainly used on the domain of academic research for a long time, if anything it may see some adoption on some mobile devices, or most likely IoT applications.

It's too late for a non x86 part to make a dent on the desktop/laptop space.

Reply Score: 5

RE[2]: Adoption
by dungsaga on Sat 18th Nov 2017 08:49 UTC in reply to "RE: Adoption"
dungsaga Member since:
2005-07-12

Open source CPU will gain adoption in server/cloud platforms. Google and Rackspace already have open server using POWER9 CPU.
More info: "Introducing Zaius, Google and Rackspace’s open server running IBM POWER9" (https://cloudplatform.googleblog.com/2016/10/introducing-Zaius-Googl...)

Reply Score: 3

RE[3]: Adoption
by jockm on Mon 20th Nov 2017 02:32 UTC in reply to "RE[2]: Adoption"
jockm Member since:
2012-12-22

Open source CPU will gain adoption in server/cloud platforms. Google and Rackspace already have open server using POWER9 CPU.
More info: "Introducing Zaius, Google and Rackspace’s open server running IBM POWER9" (https://cloudplatform.googleblog.com/2016/10/introducing-Zaius-Googl...)


Zaius is an open design, but POWER9 is not open itself. RISC-V is open all the way down to the RTL

Reply Score: 2

RE[4]: Adoption
by dungsaga on Tue 21st Nov 2017 11:02 UTC in reply to "RE[3]: Adoption"
dungsaga Member since:
2005-07-12

POWER9 is not open source. My bad.

Reply Score: 1

RE[2]: Adoption
by oiaohm on Sat 18th Nov 2017 10:54 UTC in reply to "RE: Adoption"
oiaohm Member since:
2009-05-30

It's too late for a non x86 part to make a dent on the desktop/laptop space.


This is not 100 percent sure. The ability for new cpu to enter market space are becoming more possible. Its all about the nm limit. We cannot keep on going smaller forever

3nm production is targeted to come on line for 2019. After that 1 nm and 0.5 nm might be possible. Then that is it. Then it will be focus on how the chip is internally designed and longer development cycles.

So it might not be possible for a non x86 at the moment but 5 to 10 years after silicon production hits limit all bets will be off particularly as production costs start to drop.

Risc-v chips form SiFive are already appearing in devices. You see the first chips in 2016 and the first IoT devices using Risc-v are already on the market.

Reply Score: 3

RE: Adoption
by zima on Sun 19th Nov 2017 13:56 UTC in reply to "Adoption"
zima Member since:
2005-07-06

What would it bring that ARM designs don't? And so far the latter didn't have much luck in breaking x86 monopoly on the desktop/laptop...

Reply Score: 3

RISC-V processor development
by Zoid on Fri 17th Nov 2017 21:00 UTC
Zoid
Member since:
2008-08-10

It looks like the Indian Institute of Technology is making a few versions of the RISC-V processor:

https://factordaily.com/india-chip-design-shakti-iit-madras/

Reply Score: 2

RE: RISC-V processor development
by dsmogor on Mon 20th Nov 2017 09:48 UTC in reply to "RISC-V processor development"
dsmogor Member since:
2005-09-01

That was my 1st though, BRICS countries insitutions are the first candidates to take this on seriously.
China have made their mind on mips some times ago but I bet they are looking into the arch right now.

Reply Score: 2

Performance of RISC-V
by Darkmage on Fri 17th Nov 2017 23:30 UTC
Darkmage
Member since:
2006-10-20

What sort of performance are we talking about with RISC-V? Can this thing drive a graphics card and deliver VR capable 3d? Is it basically an academic toy? I understand the need and desire for a 100% open CPU platform, I want to know where we're at and how useful this can be. There's not exactly a lot of Moore's law left to go. Architecture optimisation is going to become the new way to get performance.

Reply Score: 3

RE: Performance of RISC-V
by Brendan on Sat 18th Nov 2017 11:10 UTC in reply to "Performance of RISC-V"
Brendan Member since:
2005-11-16

Hi,


What sort of performance are we talking about with RISC-V?


Probably just plain bad performance. It's RISC (which typically means instructions are a little bit faster but you need 4 times as many instructions to get anything done); it's relatively new (which means that it hasn't had years of micro-architecture improvements); and it's not from a huge company (which in today's world of patents, means that they're prevented from using anything "state of the art").

Can this thing drive a graphics card and deliver VR capable 3d?


No, not in the way you're thinking (to do the actual processing). However (ironically) NVidia are using it in their latest video cards as a kind of scheduler (to manage which jobs are sent to which parts of the GPU).

Is it basically an academic toy? I understand the need and desire for a 100% open CPU platform, I want to know where we're at and how useful this can be. There's not exactly a lot of Moore's law left to go. Architecture optimisation is going to become the new way to get performance.


At this stage; I wouldn't consider it an academic toy.

Understand that there are a lot of different design goals for CPUs. For some (e.g. desktop) you want very good performance on single-threaded branchy code and don't care too much about design costs or extremely low power consumption. For others (e.g. GPU) you just want lots of floating point calculations in parallel, and don't care much about single-thread branchy code or extremely low power consumption. For others (e.g. smartphones) you care a lot about extremely low power consumption.

I think RISC V will be used for cases where the main thing you care about is design costs (and not single-threaded performance or lots of floating point or power consumption). Mostly, I think it'll be embedded deep inside things like chipsets and hard drives and TVs; where the main benefit is that you can "cut & paste" the CPU into a larger chip without paying licence fees to ARM.

- Brendan

Reply Score: 3

RE[2]: Performance of RISC-V
by JLF65 on Mon 20th Nov 2017 15:36 UTC in reply to "RE: Performance of RISC-V"
JLF65 Member since:
2005-07-06

The instruction set for RISC vs CISC only mattered when CPUs were MUCH faster than their data bus and relied on internal caches for the bulk of their speed. Modern buses can move data faster than the CPU can process it, and even if they didn't modern caches are huge, so RISC needing 4X as many instructions (and that's debatable) hasn't mattered for years.

The speed of a processor is solely dependent on how good the internals are... branch prediction, out of order execution, scheduling to multiple execution units, out of order data fetch and store, etc. RISC-V is just a spec with a (relatively) simple example core meant for FPGAs. Until a major company dumps significant money into the guts, it'll be slow.

Reply Score: 2

RE: Performance of RISC-V
by oiaohm on Sat 18th Nov 2017 11:27 UTC in reply to "Performance of RISC-V"
oiaohm Member since:
2009-05-30

There are 32 and 64 bit Risc-V chips already these are competitive with arm at the same nm. Talks the same kind of buses at the soc level.

The pro-type boards for the 64 bit Risc-V has pci-e support.

Performance is the same camp as Arm64 so not bad.

So the Risc-V design goes to a full proper 128bit processor. That is 128bit address space with 128bit registers and all forms of operations in those registers. We have not seen ASIC of 128 bit yet there are ASIC of 32 and 64 Risc-V.


In register count Risc-V matches SPARC, arm64 and mips cpus this is 1 under a powerpc chip in integer. Quite a few more integer registers than a x86 chip. This is 31 integer registers and 32 floating point.

Things will get interesting if we see ASIC 128bit Risc-V.

Reply Score: 1

RE[2]: Performance of RISC-V
by viton on Sat 18th Nov 2017 22:24 UTC in reply to "RE: Performance of RISC-V"
viton Member since:
2005-08-09

Performance is the same camp as Arm64 so not bad.
ARMv8 varies from single-issue micro controllers to wide Apple cores or server cores with hundreds GB/s of bandwidth.
Which ARM64 core are you referring to?

Risc-V Rocket core is competitive to Cortex-Mx microcontroller, but not to even slowest A53 core.

Edited 2017-11-18 22:25 UTC

Reply Score: 4

RE[3]: Performance of RISC-V
by zima on Sun 19th Nov 2017 14:10 UTC in reply to "RE[2]: Performance of RISC-V"
zima Member since:
2005-07-06

Cortex-Mx are ARM64/64-bit? O_o

Reply Score: 2

RE[4]: Performance of RISC-V
by viton on Mon 20th Nov 2017 04:43 UTC in reply to "RE[3]: Performance of RISC-V"
viton Member since:
2005-08-09

Cortex-Mx are ARM64/64-bit? O_o

I didn't said that. ARMv8-M for microcontrollers is 32-bit (Cortex-M22/33)

Reply Score: 2

RE[5]: Performance of RISC-V
by zima on Tue 21st Nov 2017 23:29 UTC in reply to "RE[4]: Performance of RISC-V"
zima Member since:
2005-07-06

Oh well, I just got that impression from "Which ARM64 core are you referring to?" / as if it applied to all cores you mentioned a sentence earlier... NVM then. ;)

Reply Score: 2

RE[3]: Performance of RISC-V
by oiaohm on Mon 20th Nov 2017 01:19 UTC in reply to "RE[2]: Performance of RISC-V"
oiaohm Member since:
2009-05-30

https://hackaday.com/2017/10/04/sifive-announces-risc-v-soc/
64 bit version of a risc-v here per core performance matches to a A35 core yet it under half the size of a A35 core. Yes A35 is a arm64 core.

Yes per core A53-A73 are faster. Per area of silicon not so much because you can stuff a lot more risc-v cores in the same area. If you are talking consumed silicon area the current generations of Risc-v care competitive.

Just like arm cpu there are more than 1 risc-v design.

The Risc-v rocket is only a 32 bit version. So matching up against a Cortex-Mx that is also only 32 bit is doing quite well.

Reality here is the 64 bit Risc-v current produced is competitive with the entry level end of the arm64 directly and high end arm64 if you are working to processing power to area of silicon. Ok single threaded programs not going to be the best for the current risc-v.

Of course the optimisations that make A53+ of arm faster than the a35 per core are also not implemented in the current Risc-v in production. Those feature are for future generations of Risc-v chips.

Reply Score: 2

RE[4]: Performance of RISC-V
by viton on Mon 20th Nov 2017 05:40 UTC in reply to "RE[3]: Performance of RISC-V"
viton Member since:
2005-08-09

64 bit version of a risc-v here per core performance matches to a A35 core yet it under half the size of a A35 core.

A35 supports SIMD, hardware virtualization, trustzone, etc. How about power efficiency?

Reality here is the 64 bit Risc-v current produced is competitive with the entry level end of the arm64 directly and high end arm64 if you are working to processing power to area of silicon.

Reality here is that high-end design cost hundreds of millions USD. At this point you have much more important things to worry about than the cost of arch license.

Reply Score: 2

RE[5]: Performance of RISC-V
by oiaohm on Mon 20th Nov 2017 08:04 UTC in reply to "RE[4]: Performance of RISC-V"
oiaohm Member since:
2009-05-30

"64 bit version of a risc-v here per core performance matches to a A35 core yet it under half the size of a A35 core.

A35 supports SIMD, hardware virtualization, trustzone, etc. How about power efficiency?
"
Other than trustzone and full hardware virtualization all those features are in compact risc-v 64 bit that is half the size. And power efficiency is a little better.

Feature wise A35 and current SiFive risc-v 64bit are almost 100 percent match. Virtualisation in the risc-v can be done by full hardware or rom software. SiFive risc-v 64 bit goes for rom for virtualisation.

There are major differences risc-v is more compact because is a single instruction set. You don't have legacy formats to worry about.

There is not 32 and 64 bit instruction set. There is a single instruction set of risc-v that does from 32 to 128 bit. There is not the split between compressed and non-compressed instruction set either. Very quickly you start having a way less complex cpu core.

Next risc-v chooses Vector over SIMD. SIMD was invented first than Vector was invented latter to deal with SIMD limitations and Vector is a more compacted the instruction set to-do the same things as SIMD.

Arm64 has to keep SIMD because they have to run legacy code.

Reality here is that high-end design cost hundreds of millions USD. At this point you have much more important things to worry about than the cost of arch license.

Not always true. Across a million units every cent counts.

Reply Score: 2

RE[6]: Performance of RISC-V
by viton on Mon 20th Nov 2017 16:19 UTC in reply to "RE[5]: Performance of RISC-V"
viton Member since:
2005-08-09

Feature wise A35 and current SiFive risc-v 64bit are almost 100 percent match.

Yes and A35 is a very low-end core.

There are major differences risc-v is more compact because is a single instruction set. You don't have legacy formats to worry about.

Modern ARM server cores has no legacy support.
Apple A12 is expected to exclude 32-bit mode too.

Next risc-v chooses Vector over SIMD.
SVE

Arm64 has to keep SIMD because they have to run legacy code.
Fixed width SIMD is faster at certain things.

Not always true. Across a million units every cent counts.

Proven tools and wide industry support will save you much more.

~18 billions of ARM processors were sold in last year.

Reply Score: 2

RE[7]: Performance of RISC-V
by oiaohm on Tue 21st Nov 2017 04:41 UTC in reply to "RE[6]: Performance of RISC-V"
oiaohm Member since:
2009-05-30

"Feature wise A35 and current SiFive risc-v 64bit are almost 100 percent match.

Yes and A35 is a very low-end core.

Low end core lack of legacy. Compact cores are also used in 1024+ core design.
[q]Modern ARM server cores has no legacy support.
Apple A12 is expected to exclude 32-bit mode too.

This not no legacy.

Next risc-v chooses Vector over SIMD.
SVE


Key thing you are missing is the v in the risc-v name is a reference to vector.


Arm64 has to keep SIMD because they have to run legacy code.
Fixed width SIMD is faster at certain things.

This was dis-proven by cray a long time ago. Fixed width SIMD does not work out faster than a CPU with vector designed into the base design. Does work out faster in some cases in cpu like arm64 where both are extensions.

The key thing that is missed is there is a reason why risc-v is design go to 128bit and above in the general registers. Because in a cpu core designed for vector your general registers. General registers are directly reused for vector operations.

So a risc-v to go head to head with a a73 in single core speed you would be expect the 128 or 256 bit version.

[q]Not always true. Across a million units every cent counts.

Proven tools and wide industry support will save you much more.
"
I don't disagree. Risc-v is young. So it will take a while for it to get full set of tools under it feet.

Thing so remember here is that SIMD is from the 1960s. So by the 1980 early 1990s the core patents had died. Vector in a cpu core patents expire year 2005. Risc-v starts in 2010.

So arm instruction set problem is that it legacy. Even the new arm64 instruction set is still designed to avoid patents that no longer have to be avoided. Usage of vector in cpu core would even allow CISC instruction sets to be way more compact.

The issue here is implement vector in the cpu core properly is fairly much assured with x86, power and arm instruction sets it will require breaking the instruction sets. Risc-v being a fairly new design has the option of doing vector without the legacy overhead.

So it going to be interesting to watch Risc-v mature.

Reply Score: 2

RE[7]: Performance of RISC-V
by zima on Tue 21st Nov 2017 23:27 UTC in reply to "RE[6]: Performance of RISC-V"
zima Member since:
2005-07-06

Proven tools and wide industry support will save you much more.

Yes, however those are harder to measure (and put in spreadsheet or presentation) than licensing costs ...so I can easily see management going for lack of licensing costs with RISC-V even when engineering team would prefer to stay on ARM.

Reply Score: 2